Releasing a pin from smartpin mode issue?
ozpropdev
Posts: 2,791
in Propeller 2
Chip
I've been playing with the smartpins and noticed an issue when trying to release a pin from smartpin mode.
I can change from mode to mode with no problem but if I try to go back to standard IO mode I get no action.
In the configuration long used by PINSETM all modes have Bit 31 set high.
Is clearing bit 31 supposed to release the pin from smartpin mode?
I've been playing with the smartpins and noticed an issue when trying to release a pin from smartpin mode.
I can change from mode to mode with no problem but if I try to go back to standard IO mode I get no action.
In the configuration long used by PINSETM all modes have Bit 31 set high.
Is clearing bit 31 supposed to release the pin from smartpin mode?
'Smart pin reset test con sys_clk = 80_000_000 freq1 = 10 transition = %00101 nco_freq = %00110 dat org pinsetm mode1,#32 'transition mode pinsetx ##80,#32 setb dirb,#32 pinsety ##2_000_000,#32 '2M transitions setb dirb,#34 .busy testb inb,#32 wz 'wait for completion if_z jmp #.busy setb outb,#34 'show completion qfrac ##freq1,##sys_clk 'calc freq value getqx adra pinsetm mode2,#32 'nco freq mode pinsetx #1,#32 pinsety adra,#32 setb dirb,#32 waitx ##sys_clk * 5 '5 seconds of nco_freq clrb dirb,#32 'reset/release smartpin? pinsetm #0,#32 pinsetx #0,#32 pinsety #0,#32 'the following code doesn't work ********* setb dirb,#32 .flash waitx ##sys_clk / 2 '1 Hz flash notb outb,#32 jmp #.flash mode1 long 1 << 31 | transition << 24 mode2 long 1 << 31 | nco_freq << 24
Comments
This seems to reset the smartpin and allows standard OUTx operations to follow.
So, to go to normal mode, use $80000000 in D.
D/# = %1_DD_MMMMM_BBBB_AAAA_LL_T_PPPPPPPPPPPPP
and to acknowledge the smartpin
D/# = %0_xx_xxxxx_xxxx_xxxx_xx_x_xxxxxxxxxxxxx
May I suggest the following changes.
Arrange the configuration bits as follows
D/# = %PPPPPPPPPPPPP_T_LL_BBBB_AAAA_DD_MMMMM_0
and invert what was bit31 to be 0=load,1=ack
This world clean code up a bit.
For some of the modes that don't require any other configuration bits a simple 9 bit immediate can be used.
This eliminates the need for additional "long" declarations or using an AUGD operation.
This simplifies things a bit and "looks" more logical.
Excellent!
Right now, for SETPINx, the data shifts out from MSBs to LSBs at two bits per clock. So, if the first bit pair is non-%00, it loads the full 32 bits. Otherwise, we have a PINACK and no more data is shifted. That's why PINACK takes only two clocks.
To switch things around so that simpler smart pin modes can be configured with a 9-bit constant, I'll need to send from bottom up, with the LSBs indicating whether we have a configuration or just a PINACK.
PINACK, D/# = %xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx_00
SETPINM, D/# = %T_DD_LL_PPPPPPPPPPPPP_BBBB_AAAA_MMMMM_1
It's important to get P[7:0] into a byte registration, so that the SETBYTE instruction can be used to set the DAC or level comparator.
This way...
SETPINM #0,pin = PINACK
SETPINM #1,pin = set smart pin to normal mode
I'll incorporate these changes in the next release.
The smartpins currently pass their status through INx which is OK until you need to read the actual output state.
If for example I have a few smartpins doing some "smart stuff" and I wanted to capture pin states with the streamer I will get smartpin status instead of pin output state.
Is it possible to map the smartpin status onto the ADRx registers instead leaving INx free for actual pin state?
We use the INx bits now because they were already there and have some special qualities. I think, in most cases, if you are using a smart pin, you won't be interested in reading the state of the actual pin. It would be a lot of extra wire and logic to bring those into each cog separately and then lose the current WAITPxx and edge-detect compatibility that we have with the INx bits.
I just don't see an easy solution to what is maybe a rare use case.
No worries, thanks.
Yes, you don't even need to use a smart pin mode. Just set the A-input mux.