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Suitability (and availability) of Parallax 1-2-3 A9 FPGA boards for some preproduction - Page 3 — Parallax Forums

Suitability (and availability) of Parallax 1-2-3 A9 FPGA boards for some preproduction

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Comments

  • cgraceycgracey Posts: 13,377
    jmg wrote: »
    cgracey wrote: »
    The die pad is 10.7mm square. I'm quite sure that would be the bottom dimension, too.

    +Bonding allowance ?

    Is there a package vendor part number chosen ?
    They usually have drawings, showing the actual PCB plane exposed part of the paddle.

    eg here I find 10.3mm PAD for Amkor TQFP100EP

    http://www.amkor.com/go/epad_lqfp_tqfp

    Yeah, it must have been 10.3mm, not 10.7mm.
  • jmgjmg Posts: 14,595
    cgracey wrote: »
    Yeah, it must have been 10.3mm, not 10.7mm.

    Sometimes the inner sizes can differ slightly from the outer sizes, so die size may indeed be larger.
  • RaymanRayman Posts: 11,821
    "cgracey wrote: »
    I'd design the PCB with a ~4mm plated hole under the chip. Use partitions on the solder mask to disallow solder in that area. Then, you could reflow it OR hand solder it.

    Single hole wouldn't be so good as a thermal sink though, right?

    Or, do we not have to worry about thermal stuff?

    I've seen chips were you have to solder the central pad for thermal reasons...

  • Cluso99Cluso99 Posts: 17,429
    edited 2016-02-18 06:04
    Chip,
    A 4mm hole under the IC is massive. Sure you mean 4mm???
  • cgraceycgracey Posts: 13,377
    Ma
    Cluso99 wrote: »
    Chip,
    A 4mm hole under the IC is massive. Sure you mean 4mm???

    Maybe 3mm. It needs to be big enough for a soldering iron tip to go all the way through and touch the chip's pad.
  • cgraceycgracey Posts: 13,377
    Rayman wrote: »
    "cgracey wrote: »
    I'd design the PCB with a ~4mm plated hole under the chip. Use partitions on the solder mask to disallow solder in that area. Then, you could reflow it OR hand solder it.

    Single hole wouldn't be so good as a thermal sink though, right?

    Or, do we not have to worry about thermal stuff?

    I've seen chips were you have to solder the central pad for thermal reasons...

    A big land pattern could surround the hole.
  • Liquid flux works wonders so even with tiny thermal vias you can solder the pad although solder pasting the pad before placement is recommended if you really must use an iron. Yes, 4mm is huge and I'd rather have a good and even thermal gradient across the pad and use smaller vias.
  • Cluso99Cluso99 Posts: 17,429
    cgracey wrote: »
    Rayman wrote: »
    "cgracey wrote: »
    I'd design the PCB with a ~4mm plated hole under the chip. Use partitions on the solder mask to disallow solder in that area. Then, you could reflow it OR hand solder it.

    Single hole wouldn't be so good as a thermal sink though, right?

    Or, do we not have to worry about thermal stuff?

    I've seen chips were you have to solder the central pad for thermal reasons...

    A big land pattern could surround the hole.

    I guess a big hole would work for those who want to hand solder and do the thermal pad by hand. You would want a relief around the pad top and bottom else the pad would be hard to heat to get solder to melt onto the IC pad.
  • RamonRamon Posts: 397
    edited 2016-02-18 13:17
    jmg wrote: »
    Ramon wrote: »
    Wasn't it 3.3v? Are multiple voltage banks (2, 3, or 4) easy or feasible?

    Should be, with a VccIO pin for every 4 IO pins, that's a lot of choices.

    So all those VccIO are actually independent and not internally connected between them?

    Why so many VCC pins? for better IO pad power layout? or RF signal decoupling? or just to allow multiple VCC IO voltages?

    I was thinking more on the way some CPLD/FPGA define Input/Output pins.
    With several IO banks and the designer selects the IO voltage from those banks.

    Will It be possible for the smart pins pairs allow to select (MUX) between VCC IOs?
    To allow software selectable VCC IO. (... not sure if there is any application or good reason for doing this)
    ( & some routing challenges, with all those supply pins)

    Yes, I wouldn't ever try to use 16 different supplies.
  • cgraceycgracey Posts: 13,377
    Ramon wrote: »
    jmg wrote: »
    Ramon wrote: »
    Wasn't it 3.3v? Are multiple voltage banks (2, 3, or 4) easy or feasible?

    Should be, with a VccIO pin for every 4 IO pins, that's a lot of choices.

    So all those VccIO are actually independent and not internally connected between them?

    Why so many VCC pins? for better IO pad power layout? or RF signal decoupling? or just to allow multiple VCC IO voltages?

    I was thinking more on the way some CPLD/FPGA define Input/Output pins.
    With several IO banks and the designer selects the IO voltage from those banks.

    Will It be possible for the smart pins pairs allow to select (MUX) between VCC IOs?
    To allow software selectable VCC IO. (... not sure if there is any application or good reason for doing this)
    ( & some routing challenges, with all those supply pins)

    Yes, I wouldn't ever try to use 16 different supplies.

    All VIO's are isolated from each other. This way, you can give quiet power to a set of four pins which will be doing ADC, while giving the main 3.3V to all the othe VIO's. There needed to be multiple VIO's anyway, for keeping current low on the supplies.
  • Can you leave VIOs for unused pins unpowered, to decrease power usage and wiring complexity?

    What's the maximum VIO voltage? 3.3V? Would 5V be possible?
  • Can you leave VIOs for unused pins unpowered, to decrease power usage and wiring complexity?

    What's the maximum VIO voltage? 3.3V? Would 5V be possible?

    I would say that the maximum VIO would be around 3.3V with that process but I think that perhaps the VIO would still need power, even the core voltage of 1.8V. That's what I would allow for anyway. This package, pinout, and regulation is much more complex than the P1 where many did not dare to even unDIP their big toes over to QFP44 which is a very simple package to solder, even by had, and a very easy one to route.

  • jmgjmg Posts: 14,595
    edited 2016-02-19 01:41
    cgracey wrote: »
    Here is the final planned Prop2 pinout:

    P2_100.png

    As far as the A9 board pinout goes, that can be whatever you want.

    Looking at that pinout :

    XO sits right next to a Port pin, should that Port pin shift to become a 'shielding' VccIO instead, for better glitch immunity ?
    (Xtal pins right next to Ports is never a good idea...)

    Decoupling this package will be fine on double-sided-placement (CAPS under package), but not so easy on top side placement only.

    Should Vdd pins be available at all corners to assist PCB decoupling ?
    2 corners meet this now, Xin has to bump Vdd one over, so that is ok.
    If TESn was swapped with adjacent VDD, that would give one more corner-Vdd ?


  • RaymanRayman Posts: 11,821
    edited 2016-02-19 00:00
    If the gnd pad isn't needed for thermal reasons, it seems a 128 pin package with 28 grounds would be another option...
  • cgraceycgracey Posts: 13,377
    Rayman wrote: »
    If the gnd pad isn't needed for thermal reasons, it seems a 128 pin package with 28 grounds would be another option...

    This chip may dissipate 2 watts, full blast, so we need the thermal pad.
  • Cluso99Cluso99 Posts: 17,429
    edited 2016-02-19 05:33
    cgracey wrote: »
    Rayman wrote: »
    If the gnd pad isn't needed for thermal reasons, it seems a 128 pin package with 28 grounds would be another option...

    This chip may dissipate 2 watts, full blast, so we need the thermal pad.
    I am looking forward to see who can run it full blast ;) (doing something useful of course)
  • jmg wrote: »
    Looking at that pinout :

    Also, why there are no ground pins?
    How about grouping more pins on VccIO to get extra pins?
    Do we really need 4x VDD and 4x VccIO per side?

    Please, see the attached picture. I have choosen 8 and 16 pins per VccIO because I expect that there are some streaming instructions at BYTE and WORD level.

    I have keep 4x VDD per side, but modified the number of VccIO (grouping more pins).
    This will allow ground pins on top for easier decoupling on the same layer and also will allow to do a guard ring on crystal inputs (XO/XI).

    800 x 642 - 56K
  • RaymanRayman Posts: 11,821
    Gnd is the big center square.

    I've seen other big chips that need VDD and VDDIO all around. Guess that's needed to get power all over the chip in a low resistance path. Also, they usually want a capacitor on every power pin...
  • Rayman, Yes I knew. I was asking why there is no GND pin beside the exposed pad.

    With only GND on the exposed pad you only can do decoupling on the top layer via the corners. But middle pins VDD/VCC will need decoupling caps on the bottom side with vias (which doesn't have the lowest impedance).

    With GND pins you can do decoupling on top side without vias.
    Something that jmg previously had expresed concerns.

    The proposal reduces VIO pins from a current total number of 16 to 12, 10, or 8.
    This allows to have more pins (for GND or whatever) at strategic locations to allow easier routing layout, grounding, crystal guard ring or anything else.

    Do you really need 32x Power pins for 2 Watts dissipation? I am not sure we need so many.
  • cgraceycgracey Posts: 13,377
    Ramon wrote: »
    Rayman, Yes I knew. I was asking why there is no GND pin beside the exposed pad.

    With only GND on the exposed pad you only can do decoupling on the top layer via the corners. But middle pins VDD/VCC will need decoupling caps on the bottom side with vias (which doesn't have the lowest impedance).

    With GND pins you can do decoupling on top side without vias.
    Something that jmg previously had expresed concerns.

    The proposal reduces VIO pins from a current total number of 16 to 12, 10, or 8.
    This allows to have more pins (for GND or whatever) at strategic locations to allow easier routing layout, grounding, crystal guard ring or anything else.

    Do you really need 32x Power pins for 2 Watts dissipation? I am not sure we need so many.

    To maintain analog integrity, small groups of pins need local power sources. This makes it possible to isolate for quiet ADC operation and clean DAC output. If IR drop becomes too big, you start having multiple LSB's of noise/sag on the 8-bit DACs.

    I know this looks like overkill, but I feel really at peace about it. In our last big attempt, all our VDD was in the corners, which was not good.

    Mind you that along with these 32 power pins, there are 32 hidden down-bonds from the die down to the die paddle (GND).

    About VDD and GND, it's better to have them spread out circumferentially than necessarily be in corners. If you had to choose, it would be better to have power/ground connection in the middle of the sides than in the corners. Visualize a plus-sign that fills the square die versus an X. The X is longer and suffers more IR drop than the plus-sign.

    Anyway, I understand your reaction. I went around and around with this before landing here.
  • LeonLeon Posts: 7,620
    Are you assuming a double-sided board? With 4 layers there isn't a problem.
  • cgracey wrote: »
    I know this looks like overkill, but I feel really at peace about it. In our last big attempt, all our VDD was in the corners, which was not good.

    That is precisely what I am trying to solve. By reducing the VIO (or VDD) from 4 to 3 or 2, you will get extra pins to allow GND on the centers. Only one GND on the center among two VDD or VIO pins allows to put 2 decoupling caps on both sides. Please see the awfull diagram attached.

    Leon, double sided board? Of course !!! We didn't wanted the extra PCB cost for BGA on P2 hot. And we will try to death to make this working on a 2 layer board :)


    977 x 470 - 21K
  • kwinnkwinn Posts: 8,684
    Ramon wrote: »
    cgracey wrote: »
    I know this looks like overkill, but I feel really at peace about it. In our last big attempt, all our VDD was in the corners, which was not good.

    That is precisely what I am trying to solve. By reducing the VIO (or VDD) from 4 to 3 or 2, you will get extra pins to allow GND on the centers. Only one GND on the center among two VDD or VIO pins allows to put 2 decoupling caps on both sides. Please see the awfull diagram attached.

    Leon, double sided board? Of course !!! We didn't wanted the extra PCB cost for BGA on P2 hot. And we will try to death to make this working on a 2 layer board :)


    A double sided board with a ground pad on the top layer and a Vdd pad or rectangular ring on the bottom layer should provide adequate space for bypass capacitors as well as thermal dissipation. This pinout is also pretty good for access to the data pins as well, so board layout should be relatively simple.
  • ErNaErNa Posts: 1,489
    With my latest board I decided to have 4 layers for different reasons: 1.Signal quality can be much better. 2. Layout will be denser, so the needed area is less. But there a price point: astonishingly, in small quantities (10) 4*4" are 12.50€ to 22.50€. But at 500 the price is 1€60 to 2€39. + VAT. To me the decision is clear: I will always prefer multi layer boards. The best board for the best chip!
  • jmgjmg Posts: 14,595
    cgracey wrote: »
    Anyway, I understand your reaction. I went around and around with this before landing here.
    I think this is very close.

    What about the minor pin-swaps I suggested of TESn & Vdd and getting XO separation from Port pin (by slight move of VccIO) ?

  • jmgjmg Posts: 14,595
    Leon wrote: »
    Are you assuming a double-sided board? With 4 layers there isn't a problem.
    I think both 2L and 4L should be supported as practical.

    4L would be used where all COGs and highest MHZ and DACs / ADCs were used.
    - but it should be possible to do 2L designs, eg Digital only.

    Then there are also a couple of 2L variations
    * 2 Sided placement, allows Caps-under-package, vias between GND and Pads
    * 1 Sided placement, is the trickiest.

    VccIO's need to all be connected, but I think Vdd are bonded well internally, so it is not mandatory to decouple, or even join, every Vdd pin
    Chances are the internal milliOhms is much less than the Bond+trace on 2L PCBs
  • RaymanRayman Posts: 11,821
    Not connected every VDD? Sounds dangerous to me... But, maybe you're right.
  • jmgjmg Posts: 14,595
    Rayman wrote: »
    Not connected every VDD? Sounds dangerous to me... But, maybe you're right.
    :) Yes, it needs a little care, and I'd do a first design with 16 x bottom side caps, but then check how many are really needed.
    I doubt 16 Vdd caps are mandated on every design.
    The good thing about 16 Vdd pins is, you can probe a NC one to check the internal rail noise at that point.

  • cgraceycgracey Posts: 13,377
    edited 2016-02-20 00:38
    jmg wrote: »
    Rayman wrote: »
    Not connected every VDD? Sounds dangerous to me... But, maybe you're right.
    :) Yes, it needs a little care, and I'd do a first design with 16 x bottom side caps, but then check how many are really needed.
    I doubt 16 Vdd caps are mandated on every design.
    The good thing about 16 Vdd pins is, you can probe a NC one to check the internal rail noise at that point.

    The impedance of the circuit board traces is actually 10x less than the internal power routings on the chip, as those thin metals have 42 milliohms/square sheet resistance, at best. Most are 78 milliohms/square. That's why there are lots of power and ground bonds.

    Imagine an internal power strap, 70um wide, spanning 700um, or just two I/O pads from a VIO pin. In lowest-Z top metal of 42 milliohms/square, you'd have ten squares, yielding 0.42 ohms! The resultant IR drop starts dipping into the LSBs of a 75 ohm 8 bit pin DAC. Meanwhile, the power routing on the PCB is more like 1/10th that impedance, because the copper traces are proportionally 10x thicker than the routing metals on the chip.

    For PCB design, I think a bottom-side power ring for VDD with just four caps to ground, placed on the sides of the ring, with dual vias going up to each VDD pin would be quite sound.
  • jmgjmg Posts: 14,595
    cgracey wrote: »

    The impedance of the circuit board traces is actually 10x less than the internal power routings on the chip, as those thin metals have 42 milliohms/square sheet resistance, at best. Most are 78 milliohms/square. That's why there are lots of power and ground bonds.

    Imagine an internal power strap, 70um wide, spanning 700um, or just two I/O pads from a VIO pin. In lowest-Z top metal of 42 milliohms/square, you'd have ten squares, yielding 0.42 ohms! The resultant IR drop starts dipping into the LSBs of a 75 ohm 8 bit pin DAC. Meanwhile, the power routing on the PCB is more like 1/10th that impedance, because the copper traces are proportionally 10x thicker than the routing metals on the chip.

    For PCB design, I think a bottom-side power ring for VDD with just four caps to ground, placed on the sides of the ring, with dual vias going up to each VDD pin would be quite sound.

    The DAC is powered from Vdd, or VccIO ?
    I was thinking 4 caps would be a likely OK for most Vdd uses scenario.
    (which was why I suggested getting a Vdd pad at each corner, where practical)

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