The New 16-Cog, 512KB, 64 analog I/O Propeller Chip

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Comments

  • Heater. wrote: »
    Hey, there you have it. The container idea.

    The semiconductor equivalent of containers. Every chip is the same size and shape. Same I/O. They all end up in the same package. There might be full size, half size options. Give us whatever crap you want to put in there as long as it fits the container.

    I'm betting this is only a software tool tweak away.

    Surely it's not going to help hobbyists in the same way as we don't normally make use of shipping containers. But it might help the flow of work among many small players.

    I know, just dreaming...

    That's how these multi-project-wafer companies have been operating, all along, I think. They've standardized the plot size on the wafer, but they haven't done that with packaging.

  • cgracey wrote: »
    I requested commercial pricing from CMC for the 28nm process. I saw on CMP's site that you can get a 1.88 x 1.88 mm 28nm chip made for Euro 36,000, which isn't bad. That would have to be digital pins, only.
    OOOH. How much Hub RAM would fit on this with 16 cogs and 64 Digital I/O?
    I would happily give the analog a miss if we could get >>512KB Hub.
    In fact, since speed would be really fast, we could even forgo the smart pins here.

    If good pricing comes back, it might be worth a quick discussion to see just what would fit. Perhaps it could be a quick way to get something sooner.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • jmgjmg Posts: 13,902
    Cluso99 wrote: »
    If good pricing comes back, it might be worth a quick discussion to see just what would fit. Perhaps it could be a quick way to get something sooner.

    I doubt such diversions can actually 'get something sooner'; and would certainly delay (or is that derail?) the eventual P2 release.
    FPGAs are a more useful way to 'get something sooner'
  • JRetSapDoogJRetSapDoog Posts: 795
    edited 2015-08-18 - 01:17:55
    When can I order my 16MB, 32-cog, 64-I/O pin Propeller (napkin calculation)? Parallax could go a whole 'nother direction: an "easy-to-use" processor for small systems that would stand in contrast to ARM and Intel chips, something between microcontrollers and application processors. Two roads diverged into a wood...and I...I dug a tunnel and struck blue gold. Definitely worth at least dreaming about. Hmm...well might have to divide up those 32 cogs into two separate groups if sticking with the lazy-Susan memory scheme due to too much switching logic. But still....
  • 256-I/O pins. Get it right!
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • When can I order my 16MB, 32-cog, 64-I/O pin Propeller (napkin calculation)? Parallax could go a whole 'nother direction: an "easy-to-use" processor for small systems that would stand in contrast to ARM and Intel chips, something between microcontrollers and application processors. Two roads diverged into a wood...and I...I dug a tunnel and struck blue gold. Definitely worth at least dreaming about. Hmm...well might have to divide up those 32 cogs into two separate groups if sticking with the lazy-Susan memory scheme due to too much switching logic. But still....
    YES!!!
    64 I/O is plenty
    Perhaps with the much faster speed it would be possible to just give 4 cogs access to the new hub method, and the remaining cogs just their normal slot access.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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  • Prop 3

    Risc V (free, no-IP costs)
    Prop 2 cycle-determinant Minions

    Profit?
    ---- This space available for rent ----<br>
  • While we're dreaming, lets ditch that bulky SRAM and change up to 128MB of MRAM in the same space.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • rod1963rod1963 Posts: 752
    edited 2015-08-19 - 20:15:55
    Lets wait and see what the working silicon is like and sales figures before getting all ramped up about the P-3.

    Of course there's nothing stopping the P-3 dreamers from creating their own with Verilog versions in the meantime.




  • edited 2015-08-19 - 22:40:31
    cgracey wrote: »
    He said many engineers are averse to even using newer methodologies, which would save them tons of time, yet they still get these monster chips done.
    I wonder if it's a case of doing something yourself versus having a machine do it. If you do something yourself you can point to it and say "I did that" whereas if it's all computer generated what are you going to say then? "i pushed the button" doesn't sound very satisfying.

    Infantryman's Axiom; Always cheat, always win.
  • The latest document that Chip posted still shows the name LINK instead of CALLD. I thought it was decided to use the name CALLD for the instruction. So which one is it, LINK or CALLD?
  • jmgjmg Posts: 13,902
    edited 2015-08-20 - 04:38:13
    cgracey wrote: »
    He said many engineers are averse to even using newer methodologies, which would save them tons of time, yet they still get these monster chips done.
    I wonder if it's a case of doing something yourself versus having a machine do it. If you do something yourself you can point to it and say "I did that" whereas if it's all computer generated what are you going to say then? "i pushed the button" doesn't sound very satisfying.

    - or, it may simply be hard-won experience!.
    Far too many software "newer methodologies" have serious bugs, that some poor mug has to find the hard way.
    That claimed "save them tons of time" can often be an illusion, if rework is needed, or something falls thru the cracks.

    I know many companies that refuse to change software versions within a development cycle, and some even archive the tool version that was signed-off, as the future-maintenance tool.


  • cgracey wrote: »
    My brother took his oldest son to visit Northwestern University a few weeks ago and they had an interesting experience.

    Just to clarify, this was not at Northwestern University (NU) , but another well-known midwest engineering university [who is also a customer of Parallax]. NU was an impressive place in so many ways, which is why we collaborated on the Electronic Conference Badge and have so much respect for their programs.

    But the rest of the story is correct. The university's engineering tour reflected the massive STEM push which makes engineers out of everybody. Having been to well over a hundred universities on behalf of Parallax, I've seen inspiring programs and programs people take as their next step. What was interesting to me - at this particular university which had an inspiring program is that the high school kids in the tour just weren't getting their questions answered. I could see they were a hands-on group and they wanted to apply their skills in the new lab facilities. But when they asked the guides why they should attend this university, the answers went soft and were oriented around clubs, social activities, etc.
  • jmg wrote: »
    I know many companies that refuse to change software versions within a development cycle, ad some even archive the tool version that was signed-off, as the future-maintenance tool.

    We've taken to doing this. BTW, I recall some years ago installing a much needed tool update without bothering to inform one of the more senior engineers. He nearly bit my head off.

    Platåberget
  • Beau SchwabeBeau Schwabe Posts: 6,415
    edited 2015-08-20 - 05:44:11
    "I know many companies that refuse to change software versions within a development cycle, ad some even archive the tool version that was signed-off, as the future-maintenance tool." - There is good reason for this, and all of the big players that I know, this is just the way it is done. Period. The main reason is that you want a stable work environment so that if something does go wrong, you can minimize any variables. Changing ANYTHING mid-project such as software, process, technology, etc. is just asking for trouble. As soon as a particular project is over and you want to upgrade/downgrade or whatever ... fine do it then, but never do it mid-project.


    "...many engineers are averse to even using newer methodologies, which would save them tons of time, yet they still get these monster chips done." - This directly relates to the above explanation and has very little to do with being averse to using newer methodologies or even reverting back to older methodologies (because they happened to be cheaper) as was in my case. It has to do more with disruption of the work flow and drastic changes as mentioned above can easily brick a design.

    "Education" is key here as well ... locking yourself into a process technology, say for instance 180nm, without educational seminars for other late breaking technologies is not a smart projection plan for the overall health of a project regardless if you aren't planning on using the other late breaking technologies. The reason is that methodologies and ideas used in new technology can often be applied in current technologies if nothing more than to re-iterate and re-enforce a smart work flow thought process. Not to mention education certification along the way.



    ALL of this should be common sense engineering 101 though and I shouldn't have to break down the importance of why you lock things down and why engineers can sometimes seem stubborn in their ways. There is good reason why we do what we do.


    Beau Schwabe --- Robotics applications- PCB design, embedded software, and mechanical
    Oklahoma Robotics -

    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • pedwardpedward Posts: 1,561
    edited 2015-08-20 - 20:40:33
    Beau, I've noticed that you've been making not-so-subtle digs at Chip for a while now.

    Telling him that he's being myopic because he chose 180nm and is sticking to it, isn't a way to make friends.

    He has his reasons, and if anything, Chip is one of the most flexible people I know when it comes to input from others.
  • bartgranthambartgrantham Posts: 67
    edited 2015-08-20 - 21:44:43
    (was away for a month, then came back to a whirlwind of forum activity that took another few weeks to catch up on)

    I wanted to pick up on something from a week or two back regarding hubexec, eggbeater timing, and jumps. Without thinking it through very carefully, it seems that it would be possible for an assembler to take a stab at aligning jumps and entry points so that an entry point address is aligned to be on the next cycle for most jumps to that entry point.

    It wouldn't be possible to achieve a perfect result where everything was aligned, and you'd have to sacrifice some code space because you'd have gaps in packing the functions that now required specific alignment. But it opens up a dimension of optimization, especially for bottleneck functions.

    And as for CHKDEC/CHKHEX/CHKLET/CHKSYM from P2Hot... I agree with Heater's assessment that they're generally not worth it. He had an excellent example with DAA on x86. OTOH, didn't Chip say that these were pretty important for reducing code size of the monitor on P2? What's the minimum possible bit of workalike PASM for these 4?
  • @pedward - Chip is a big boy, and I'm just offering constructive criticism. I'm not trying to make friends, I'm trying to speak my mind. If obscurity prevents someone from speaking their mind because everyone else wants to candy coat the situation then what is the point. "My biggest concern is that the ship has has already sailed" these are not my words but words asked directly to me while still at Parallax. At the time I did not know for sure the answer to this, but since then I have had some time to think about it, and now I have an opinion. If my opinion does not agree with you, then I am sorry. There are many people that do agree with me but perhaps don't wish to say anything. That's fine also... 22 years in the forum and I have seen it all... you take everything with a grain of salt and move on.

    I will say this. A deadline needs to be set. Why? Because any project without a deadline becomes that perpetual 95% complete essay that will never get done. There will ALWAYS be something you can do differently to tweak it a little here or a little there.



    Beau Schwabe --- Robotics applications- PCB design, embedded software, and mechanical
    Oklahoma Robotics -

    www.Kit-Start.com - bschwabe@Kit-Start.com ෴෴ www.BScircuitDesigns.com - icbeau@bscircuitdesigns.com ෴෴

  • Thinking about the 300K limitation vs additional cost...

    If it's not way over the limit, perhaps drop out 1 cog and give its hub slot to another cog if it's not a lot of trouble
    Just a thought!
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
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    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Development cost was obviously a big factor in choosing 180nm. And the 300K gate limit compounds this point.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • Peter JakackiPeter Jakacki Posts: 8,641
    edited 2015-08-21 - 04:04:08
    I have the greatest respect and admiration for Chip and personal digs have no place on this forum but I agree with deadlines as all too often I will continue to improve and improve and never quite finish. The deadline gives the focus and definition. I've hit a brick wall some time ago with P1 projects and I've probably squeezed as much as I could from it while balancing the effort required to get P1 to do what I really want P2 to do which would require less effort and do it better. I've always said just "print it" so to speak and then you can play to your heart's content with designing P3.

    The greatest flurry of activity on the declining forum in the last couple of years have been around P2 features and P1V playthings, but nothing concrete that I and many others can actually use.

    I thought Parallax was also a commercial business.....yes, one that invests money to make money, but trying to make P2 a P3 before it's a P2 is not making any of us money.


    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    --->CLICK THE LOGO for more links<---
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  • Ken GraceyKen Gracey Posts: 6,458
    edited 2015-08-21 - 04:49:54
    I've enjoyed reading a few of the comments above. I understand the business planning around this effort very well since I've run Parallax through nearly 10 years of high P2 design costs while being part of an electronic market that's brought more competition and lower margins than one would have ever imagined. I also talk to Chip nearly every day about the specific stage of his design and meet with the consulting team at least twice a month. I see this puzzle from all angles, and so does Chip. He has an excellent way of focusing on engineering and sometimes OT world issues - but you will never see him engage in these softer social or business issues that come up from time to time. I'm thankful he doesn't get into this stuff, too, as it can really eat people up unless they take comments with a grain of salt (as Beau said) or with thick skin (as Phil says).

    Some of the business-oriented forum discussion above is truly dead-on; other parts are far off. But I'll confirm a few things here which are truly the case from recent posts:

    - Project management could be significantly improved (schedule, scope, features).
    - 180nm is where we can afford to design, at least with our current self-funded biz model.
    - Chip will finish the project, and wants it done more than all of you.
    - The design team includes you, from his perspective, so you better not encourage new stuff anymore. The P2 effort is really more open-source and community-designed than anything in it's class.

    Clearly, we don't do things the way a normal business would choose to do. As a result we don't have a sellable business model with the Silicon Valley "exit strategy" but this also means a few wonderful things for our customers: consistency in management and vision (unless we make the same mistakes again), long-term supply commitment, and an open process without lawyers telling us what we can share.

    I am certain P2 will be a really unique multicore chip.

    Ken Gracey
  • jmgjmg Posts: 13,902
    Ken Gracey wrote: »
    - The design team includes you, from his perspective, so you better not encourage new stuff anymore.

    From what Chip has said, the opcodes and core are pretty much completed, and as soon as Chip releases a FPGA build, work can start on testing software, software tools, and verifying use-cases of the working opcodes.
    That milestone should be relatively easy to deadline. Real Soon Now ?

    I would also expect minor fixes to those opcodes and iterations of a few FPGA builds as issues are uncovered. (in parallel with Smart Pins development)
    That is a little harder to deadline. Good test coverage takes time.



  • Thanks for the update Ken.

    I'm up to my armpits in arm dev boards but keep holding off as I really want P2. I want it, you want it, customers want it, Chip wants it, and yet we are still in want. At this late stage the P2 is going to be what the P2 is, no rationalizations, no unnecessary fluff, just P2.2015/16. However if I knew that P2 would not be available even in 2015 I probably would have ARMed myself fully years ago. But the fact that we are still here must indicate something, not so much about us, but about our faith in Parallax and our hope for P2.

    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    --->CLICK THE LOGO for more links<---
    P2 +++++ TAQOZ INTRO & LINKS +++++ P2 SHORTFORM DATASHEET
    P1 +++++ Latest Tachyon includes EASYFILE +++++ Tachyon Forth News Blog
    Brisbane, Australia
  • jmgjmg Posts: 13,902
    Ken Gracey wrote: »
    I also talk to Chip nearly every day about the specific stage of his design and meet with the consulting team at least twice a month.

    Curious if OnSemi have run any test wafers of the Custom-design stuff (ADC/DAC/Fuses?), or do they (you?) have enough confidence in their Simulation tools ?

  • Cluso99Cluso99 Posts: 15,396
    edited 2015-08-21 - 05:34:43
    Ken Gracey wrote: »
    I've enjoyed reading a few of the comments above. I understand the business planning around this effort very well since I've run Parallax through nearly 10 years of high P2 design costs while being part of an electronic market that's brought more competition and lower margins than one would have ever imagined. I also talk to Chip nearly every day about the specific stage of his design and meet with the consulting team at least twice a month. I see this puzzle from all angles, and so does Chip. He has an excellent way of focusing on engineering and sometimes OT world issues - but you will never see him engage in these softer social or business issues that come up from time to time. I'm thankful he doesn't get into this stuff, too, as it can really eat people up unless they take comments with a grain of salt (as Beau said) or with thick skin (as Phil says).
    I am truly pleased that Chip does not take the comments to heart. Some have been OTT.
    Some of the business-oriented forum discussion above is truly dead-on; other parts are far off. But I'll confirm a few things here which are truly the case from recent posts:

    - Project management could be significantly improved (schedule, scope, features).
    - 180nm is where we can afford to design, at least with our current self-funded biz model.
    - Chip will finish the project, and wants it done more than all of you.
    - The design team includes you, from his perspective, so you better not encourage new stuff anymore. The P2 effort is really more open-source and community-designed than anything in it's class.
    Maybe it's true that project management could be improved. But Parallax has other things to do concurrently with this, and if they don't achieve the attention required there might be no funds left to fund the P2. As outsiders, we do not have all the info to legitimately criticise.

    From comments on this forum and what I have read, I can see why 180nm seems to be the best process for the P2.
    But it's always nice to dream what 14nm or other processes could achieve.

    We are all pleased to be able to be involved in the design input, even if we stray from the requirements at times :(
    Point taken though... no new stuff ;)
    Clearly, we don't do things the way a normal business would choose to do. As a result we don't have a sellable business model with the Silicon Valley "exit strategy" but this also means a few wonderful things for our customers: consistency in management and vision (unless we make the same mistakes again), long-term supply commitment, and an open process without lawyers telling us what we can share.
    Just because you don't do things like a normal business does not mean the business is not saleable. But that is not what you want now, so it's irrelevant anyway.
    I am certain P2 will be a really unique multicore chip.

    Ken Gracey
    The P2 will definitely be unique. Here's hoping it finds lots of commercial apps to get the volumes up and recoup the investment.

    Ray

    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • jmg wrote: »
    Ken Gracey wrote: »
    I also talk to Chip nearly every day about the specific stage of his design and meet with the consulting team at least twice a month.

    Curious if OnSemi have run any test wafers of the Custom-design stuff (ADC/DAC/Fuses?), or do they (you?) have enough confidence in their Simulation tools ?

    Chip passed Treehouse some files a week ago and they've run them but I'm not aware of the results. I think there was some sort of hiccup related to tools, but maybe not - I'll need to ask Chip again but I've certainly seen some activity on this end.

    If I knew P2 wouldn't be available until 2015 or beyond I would have also managed Parallax quite differently. Some of the things I'd have considered include a fully-integrated approach towards Arduino educational content, earlier multi-platform tool development for P1, delay of any P2-oriented C compiler efforts, and so on. Hindsight is 20/20 but we also can't drive the car forwards while looking in the rear-view mirror (if that makes any sense - it does in my mind). We made it here and we shall finish.

    Ken Gracey
  • Ken GraceyKen Gracey Posts: 6,458
    edited 2015-08-21 - 05:44:26
    And about simulation tools and our level of confidence. Yes, I have confidence in this round. Having been part of two prior efforts where the schematic layout/synthesis integration being disconnected, and discussing my concerns over and over again like an accountant who knows just enough to annoy the engineers, I'm pretty sure the software simulation tools and team we've got in place will work properly. We're not interested in another failed attempt so I'm asking questions about anything and everything along the way.

    Ken Gracey
  • jmgjmg Posts: 13,902
    Ken Gracey wrote: »
    And about simulation tools and our level of confidence. Yes, I have confidence in this round. Having been part of two prior efforts where the schematic layout/synthesis integration being disconnected, and discussing my concerns over and over again like an accountant who knows just enough to annoy the engineers, I'm pretty sure the software simulation tools and team we've got in place will work properly. We're not interested in another failed attempt so I'm asking questions about anything and everything along the way.

    Ken Gracey
    Simulation confidence can be related to how close a design they have passed before, that also measured very close to what simulation said.
    The greater that divergence from proven pathway, the greater the risk.

    Do OnSemi have a prototype/test wafer service/flow ?

    What about Fuse handling - IIRC that was a custom literal 'burn' in the older design, but that probably does not simulate well ? ;)
    Where does that leave User Fuse support ?



  • Ken,
    Some of the things I'd have considered include a fully-integrated approach towards Arduino educational content
    Ouch!

    We can be grateful for small mercies I guess. That was close.
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