Sadly I think I hear the sound of bullets bouncing of the walls again!
Oh, I hope not in this case! I hope that this suggestion might actually result in a simpler (but not necessarily fewer gates) implementation of the cogs. Of course, everything always works perfectly "in theory". And I suspect that there's a sizable gap between my "theory" and Chip's "reality". And there might be a good middle ground, as well. For instance, it might be possible to make the INDx-handling changes in the pipeline, while still using the COND bits. We wouldn't get conditional execution, but we would still get task-safe INDx (including a fix for the self-jump "issue"),
There is an extra 1-bit flag register (per cog).
0: When reset (default and init state) the INDn acts as they do now: No cond codes; INDn/IND++/IND--/++IND
1: When set: WIth cond codes and INDn only (ie No auto inc/dec)
This requires:
(1) Either FIXINDn instructions to be extended to include a set/reset the above flag bit
or a new CFGINDn instruction to set/reset the above flag
(2) A new instruction(s) INCINDn/DECINDn to perform INDn++, IND-- and obeys the max/min wrap of FIXINDn settings
This keeps everything as it is now, plus allows the user to give up the auto inc/dec for full access to the condition codes (all 16 conds) on a per cog basis. It can also be dynamically be changed (with a delay of course to clear the pipe). This also permits overcoming some of the issues of multitasking.
Comments
Oh, I hope not in this case! I hope that this suggestion might actually result in a simpler (but not necessarily fewer gates) implementation of the cogs. Of course, everything always works perfectly "in theory". And I suspect that there's a sizable gap between my "theory" and Chip's "reality". And there might be a good middle ground, as well. For instance, it might be possible to make the INDx-handling changes in the pipeline, while still using the COND bits. We wouldn't get conditional execution, but we would still get task-safe INDx (including a fix for the self-jump "issue"),
There is an extra 1-bit flag register (per cog).
0: When reset (default and init state) the INDn acts as they do now: No cond codes; INDn/IND++/IND--/++IND
1: When set: WIth cond codes and INDn only (ie No auto inc/dec)
This requires:
(1) Either FIXINDn instructions to be extended to include a set/reset the above flag bit
or a new CFGINDn instruction to set/reset the above flag
(2) A new instruction(s) INCINDn/DECINDn to perform INDn++, IND-- and obeys the max/min wrap of FIXINDn settings
This keeps everything as it is now, plus allows the user to give up the auto inc/dec for full access to the condition codes (all 16 conds) on a per cog basis. It can also be dynamically be changed (with a delay of course to clear the pipe). This also permits overcoming some of the issues of multitasking.