BeMicro CV FPGA Board for P2 ?

jmg · 2013-10-15 12:47

I think this needs a new thread

New BeMicro CV FPGA Board : just $49.* (Verical shows 22 in stock, at $42.03, orderable 1+ )

http://newsroom.altera.com/press-releases/nr-low-cost-dev-kits.htm

Runs a Cyclone V (5CEFA2F23C8N)

Includes SD slot
DDR3 64M x 16 MT41J64M16LA @ 300MHz [ Micron DDR3 SDRAM 1G (64M x 16) 533MHz]
has 0.1" headers ( 20x2 in 2 strips) and a 80 pin edge connector.
4.5 V ~ 15 V ADP5052 Switching regulator & power Jack
48mm x 92mm (similar to Quickstart size of 51mm x 76mm)

What speed would a P2 build hit on this, and how much HUB RAM could it give ?

Bill Henning · 2013-10-15 13:08

It looks interesting, but only seems to have enough LE's for one cog.

Using the M10K blocks for hub it looks like 176KB of HUB would be possible.

http://ca.mouser.com/ProductDetail/Altera-Corporation/5CEFA2F23C8N/?qs=sGAEpiMZZMs022Iw/oIyCwzG6hZaHCdf

Product: 	Cyclone V E 	
Number of Logic Elements: 	25 K 	
Number of Logic Array Blocks - LABs: 	9434 	
Total Memory: 	1956 kbit 	
Number of I/Os: 	224 	
Operating Supply Voltage: 	1.1 V 	
Maximum Operating Temperature: 	+ 70 C 	
Mounting Style: 	SMD/SMT 	
Package / Case: 	FBGA-484 	
Embedded Block RAM - EBR: 	196 kbit 	
M10K Memory: 	1760 kbit 	
Maximum Operating Frequency: 	800 MHz

Also the P2 Verilog does not support DDR3.

Bill Henning · 2013-10-15 13:12

http://www.altera.com/products/devkits/altera/kit-terasic-cyclone-v-gx-starter.html

Looks MUCH More interesting for $179

- Three cogs would not be a problem
- 488KB hub possible

jmg · 2013-10-15 13:53

Bill Henning wrote: »

Looks MUCH More interesting for $179

- Three cogs would not be a problem
- 488KB hub possible

Yes, but many cannot afford $179, so the most compact and cheapest way to run P2 (even one COG) is an important entry point.

Also the P2 Verilog does not support DDR3.

not yet...

nutson · 2013-10-15 14:37

Come on, how many different FPGA configurations do you want Chip to maintain? He is already supporting 3 FPGA versions of the P2 (the Stratix III he is using himself, and the DE0-nano and the DE2-115). This new board you spotted can only support one Cog, I don't see any reason to request Chip do do the effort to port the P2 design to this board just to add another crippled P2 solution besides the DE0-nano just to help users save a few bucks. I want silicon ASAP.

The board Bill found is a little more interesting. It could carry a 3-4 COG solution at about 1/3 the price of the DE2-115. If this would attract a significant number of designers stepping in and start experimenting with multi-COG software and drivers, and thus advance P2 software development, only if this is proven in advance, I would vote "yes" for yet another P2 emulation board.

jmg · 2013-10-15 16:11

nutson wrote: »

I want silicon ASAP.

As does everyone, but these FPGA boards are not on the Silicon critical path, but they will be important for SW-ready tools when the Silicon does eventuate.
The DE0-nano comes up short on Memory, and it makes sense to track the best-value FPGA boards, as time passes.

Cluso99 · 2013-10-15 16:17

nutson wrote: »

Come on, how many different FPGA configurations do you want Chip to maintain? He is already supporting 3 FPGA versions of the P2 (the Stratix III he is using himself, and the DE0-nano and the DE2-115). This new board you spotted can only support one Cog, I don't see any reason to request Chip do do the effort to port the P2 design to this board just to add another crippled P2 solution besides the DE0-nano just to help users save a few bucks. I want silicon ASAP.

The board Bill found is a little more interesting. It could carry a 3-4 COG solution at about 1/3 the price of the DE2-115. If this would attract a significant number of designers stepping in and start experimenting with multi-COG software and drivers, and thus advance P2 software development, only if this is proven in advance, I would vote "yes" for yet another P2 emulation board.

Totally agree.
While $500+ for a DE2 is expensive, the $179 that Bill referenced is well within the range of those who are serious about helping the P2 development. It is a better prospect than the DE0 because we can run at lest 2 cogs and hopefully get the full 128KB of hub.
The whole idea is to get those who know the P1 well to help find problems, and get P2 tools ready, before the real P2 is available. Its not meant as a toy for people to play with.

ozpropdev · 2013-10-15 18:11

Hi Guys

I believe the whole FPGA emulation program has been a incredible success!
The amount of valid data that has been collected over the last 12 months has been pivotal in
important tweaks being made to the design. Echoing everyone "we all want silicon", but if a few
months wait means we get even better silicon then i'm all for it.

My Invaders code may be seen as a pointless/trivial waste of time, but when examined closely
it highlights the massive potential of the P2 and it's cool features. I don't know about anyone else
but I certainly learnt a lot from it and am now applying what I've learnt into "serious" stuff.

I recently updated to a DE2 board from the DE0 mainly for one reason.. 128k Hub ram.
Sure more Cogs is nice too. I agree that the DE2 is expensive, but in the end its a valuable tool
and is far better/easier option than writing a software emulator.

If other FPGA options become available for more people to get involved we all win!

As a fellow Propeller Head I feel it's my DUTY to play with the toys that Chip provides us!

Tubular · 2013-10-15 19:38

One interesting aspect I don't think anyone has mentioned - the two 0.1" headers are pin compatible with the DE0 Nano. That means parallax's existing DE0 breakout board should work without hardware revision.

I think "the goal" is to find bugs, get feedback on improvements, and keep parallax fans/early adopters keenly developing while we wait for silicon. Bugs and feedback are priceless and the more that can be found at this stage right now, the better.

In some ways this is too cheap - ideally you want developers who will push the hardware to flush out the issues, rather than putting it in a drawer in case its handy one day. But if this cyclone 5 supports 128kB hub ram, that would be a huge win compared to the DE0-Nano. Faster clock speed would be a bonus, SDRAM support may not be missed for many.

I'll be doing a P2 to DE0-Nano breakout board for when P2 silicon arrives (if no-one else does). While that will be nominally to replace the DE0-Nano/BeMicroCV, it would be possible to stack both, which would be interesting for USB3 or LVDS development, for instance

I've ordered one... thanks JMG for bringing it to our attention quickly.

rjo__ · 2013-10-15 20:56

Something we all know, but hasn't been said in relation to migrating FPGAs is that once the silicon for the P2 is done and the product is well launched, Chip has said would like to start an open FPGA initiative, based around a big board design for the P3. The other idea that seems to have some traction is to have a P2 in Silicon on a big FPGA board, which might also be a P3 host. So the question is... how many rounds of FPGA migration are we going to need?

What I did was to buy a Nano to get familiar with everything, with plans to purchase a the DE2-115, when SPIN2 was released... assuming that would happen before the final silicon. Chip is hot and heavy on this, and I am just about ready to get another board, I do need the extra hub space, and I certainly wouldn't mind having 5 cogs. I like the $179 version because it also has a nice HDMI connector... but I like the $279 Terasic board because I think it would be a hoot to have all of that memory access and control. And while the P2 might not be able to tap into some of that memory, the P3 probably will. I see one or both of these boards as good candidates for a generic... non-Parallax... P3 FPGA candidate. I don't know what to think about the BeMicro device. I like it and if I was looking around for a really inexpensive way to get into FPGAs, I would certainly consider it. But in this context, the fact that it uses a different development environment (which looks very nice) is an issue. I wouldn't want to migrate from an environment that I am barely familiar with to something completely new and then back again when the P3 project starts.

Leon · 2013-10-16 06:47

I've ordered one from Verical. I'm not interested in using it in connection with the P2, but want a cheap way to play with the Cyclone V.

Leon · 2013-10-17 03:15

Here is the Arrow web page describing the new kit:

http://components-asiapac.arrow.com/en/campaign/altera-bemicro-cv-fpga-development-kit/

Gerber files are available, but I doubt if anyone would want to get their own board made; it looks as though it has six layers.

Ale · 2013-10-18 00:39

I had dreams about that board ( the BeMicro CV) like the whole last night... I may need to go out a bit more... and get one of those boards

Bill Henning · 2013-10-18 06:24

I'm going to get one of the $49 BeMicro's for playing with Verilog. I really like all the exposed .1" headers; and for I/O experimens, I'd much rather take chances with a $49 board... and it has a LOT more logic than the cheap EPM240 and EPM570 CPLD's.

David Betz · 2013-10-18 07:07

I have the Verilog code for a processor we designed at VM Labs back when Eric Smith and I worked there. The IP is now owned by STMicroelectronics but they have given permission to release the code under the MIT license. I haven't even tried to compile it yet but it would be fun to get it working on an FPGA. Also, this was used in an early multi-core chip that had four of these processors on it. Even better, there is a port of GCC to it done by Eric Smith and Ken Rose! If anyone here would like to help bring this up on an FPGA please let me know.

Ramon · 2013-10-18 07:27

JMG, Thanks for the link.

That was the kind of board I wanted as a Cyclone V Terasic´s DE0-nano upgrade. Cheaper, 4x more memory, more IO pins.

Does anyone knows if the FPGA IC can be desoldered and upgraded with one with more logic (but within the power consumption limits of the power sourcing ICs)? It's this feasible? Does anyone have this kind of tool?

Leon, even if 6 layer is possible there are some problems (cost and embedded JTAG). The FPGA IC costs $43.66 at mouser and digikey. The embedded USB-JTAG use a MAX V (5M80ZE64C5N). I think is factory programmed and there is no way to get either the code or binary file.

About cost: I have prepared a BOM list. I wonder what would be the quote for all the components. If anyone can beat $42.03 USD, please raise your hand.

rod1963 · 2013-10-18 09:49

Ramon

Don't even try it. You'll simply destroy the BeMicro board. The fact is the average hobbyist doesn't have the equipment nor skills to handle big bga's.

If you need bigger, it's cheaper to open your wallet and buy a bigger eval board.

Heater. · 2013-10-18 10:13

Quit likely you will destroy your board trying to unsolder the FPGA chip and replace it.

Also have you checked that there is actually a larger capacity chip with the same pin out?

base2design · 2013-10-18 11:46

David, is this the NUON stuff? Wow... how big of a FPGA would be needed for this?

Bill Henning · 2013-10-18 11:53

That sounds extremely interesting... now if I could only find the time to dive in...

David Betz wrote: »

I have the Verilog code for a processor we designed at VM Labs back when Eric Smith and I worked there. The IP is now owned by STMicroelectronics but they have given permission to release the code under the MIT license. I haven't even tried to compile it yet but it would be fun to get it working on an FPGA. Also, this was used in an early multi-core chip that had four of these processors on it. Even better, there is a port of GCC to it done by Eric Smith and Ken Rose! If anyone here would like to help bring this up on an FPGA please let me know.

David Betz · 2013-10-18 12:10

Bill Henning wrote: »

That sounds extremely interesting... now if I could only find the time to dive in...

Yeah, that's my problem too. :-(

Heater. · 2013-10-18 13:02

David,

Don't tell me you have another CPU we can emulate on the Propeller!

David Betz · 2013-10-18 13:08

Heater. wrote: »

David,

Don't tell me you have another CPU we can emulate on the Propeller!

This one probably isn't a good candidate for emulation. It's a VLIW processor that can execute several instructions in a single clock. It's called the MPE which stands for Media Processing Element. I can post the instruction set if you''re interested. What I really want to do is get it running on an FPGA so I can upload it to Open Cores.

Heater. · 2013-10-18 22:02

Interested, yes. No time or verilog skills available here though.
Open Cores does sound like a good home for it. Having a compiler available for it should make it interesting to many.

Leon · 2013-10-19 03:04

I've received an email from Verical with a DHL tracking number. The kit has arrived in the UK and is on its way to the Maidstone depot, I should get it on Monday.

David Betz · 2013-10-19 05:39

Heater. wrote: »

Interested, yes. No time or verilog skills available here though.
Open Cores does sound like a good home for it. Having a compiler available for it should make it interesting to many.

I've played with Verilog a little and would like to learn more but I feel as though porting a processor to a new platform is beyond my current abilities and time. I've been unsuccessful in getting any of the former VM Labs people interested in helping and I don't really want to dump a bunch of Verilog code onto Open Cores without a working example. I guess that means that this IP will likely never get released. Maybe that's why there isn't more open source hardware out there.

Sapieha · 2013-10-19 05:52

Hi David.

I can test port it to NANO ---- If You then test program and run it

David Betz wrote: »

I've played with Verilog a little and would like to learn more but I feel as though porting a processor to a new platform is beyond my current abilities and time. I've been unsuccessful in getting any of the former VM Labs people interested in helping and I don't really want to dump a bunch of Verilog code onto Open Cores without a working example. I guess that means that this IP will likely never get released. Maybe that's why there isn't more open source hardware out there.

Ramon · 2013-10-19 08:31

rod1963: I know. I asked if anyone here has the knowledge and tools for rework/reballing. I like the small size of DE0-nano and BeMicro CV.

Heater: I have checked that 5CEFA2 (25K LE) and 5CEFA4 (49K LE) has the same pinout. Higher density FPGAs (5CEFA5 and 5CEFA7) seems to have different pinout than 5CEFA2.

5CEFA4 cost $59.80 (digikey and mouser has the same price). So even if possible, maybe not worth (economically) to do it.

If Arrow had made the board with 5CEFA4 I wouldn't mind pay some extra $ for 2x more logic elements.

Heater. · 2013-10-19 08:34

David,

Perhaps whilst it's not "ready to rock" on an FPGA you could put put all the sources of MPE on github or somewhere. Where people can look it over at least and it won't get lost. Who knows what happens next?

rod1963 · 2013-10-19 11:04

Ramon

Just buy the Terasic Cyclone V GX Starter Kit for $179.00 instead of paying someone you know nothing about to hack and probably destroy your BeMicro board.

Ale · 2013-10-20 04:49

Hei Leon, did you buy by arrow.com ? Don't they have a UK site ?... (I thought they had one in Germany too...).. I'm going to get one of those kits...

BeMicro CV FPGA Board for P2 ?

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