CMOS and TTL signal voltage levels?

Archiver

Can anyone tell me what the actual specs are for a 'high' CMOS/TTL signal?
What is the minimum voltage for each? A customer is trying to interface to
our equipment with what I feel is a flaky signal...

Duncan

Archiver

> Can anyone tell me what the actual specs are for a 'high' CMOS/TTL
> signal?
> What is the minimum voltage for each? A customer is trying to interface
> to our equipment with what I feel is a flaky signal...
> > >
> > > Duncan
> >
With TTL: A logic-high output should be at least 2.4V. A logic-high input
at least 2V.

CMOS is quite a bit different. Working with a 5V supply, a CMOS logic-high
output is at least 4.9V, and a logic-high input must be at least 70% of the
power supply, or 3.5V with a 5V supply.

Thanks to Jan Axelson for this data. It came directly from her book
'Serial Port Complete". Lots more than just serial information in
this book..;o]

Regards,

Bruce Reynolds

Reynolds Electronics
633 N. 8th St.
Canon City, Co. 81212
Voice: 719-269-3469
Fax: 719-276-2853
http://www.rentron.com

Archiver

> Can anyone tell me what the actual specs are for a 'high' CMOS/TTL
signal?
> What is the minimum voltage for each? A customer is trying to interface
to
> our equipment with what I feel is a flaky signal...

Are you asking about BASIC Stamp inputs? The input thresholds I have seen
(albeit in a relatively small sample) have been very close to 1.3 volts.
The PIC16C57 data sheet states that the threshold shall in any production
run be within the range from 1 to 2 volts on a 5 volt power supply over the
speced commercial or industrial temperature range. The noise margin is of
course best if the input signal comes from a low impedance source and
swings clean and fast between 0 and 5 volts.