Cluso's NanoBlade2 (digressed to DIP40 discussion)

2

Comments

  • Peter JakackiPeter Jakacki Posts: 9,811
    edited 2020-11-02 - 13:55:37
    So the P2 is a product of what the customer really wants, or is it a product of an engineer who knows that what the customer needs is not what the customer think they want? How many times have I discreetly over-engineered a design to be flexible and modular because the customer insists that "this" is what they want and nothing more. However they never really understand the problem until the real solution is provided, which is why I am able to save the day when the goods supplied to spec fulfills the customer's want but fails to provide the solution that the customer needs. or perhaps the customer's customer etc.

    Impossible to do this 0.3" layout efficiently or well although you could add a few extra layers to do it. Personally I think that constantly providing bleeding edge technology in limp and lame packaging makes no sense at all and borders on absurdity. If it did make sense then we'd still be using octal sockets because they were the original standard for any serious project. Let's see, a P2 in an octal socket? Impossible!? Of course it isn't impossible, just totally absurd. Let's free ourselves of this 70's DIP and "solderless breadboard" nonsense once and for all by not being a party to it. The very least a breadboard manufacturer could do is make the sockets handle pin headers better and have wider breadboards and better power rails, but they are supplying exactly what "the customer wants".

    BTW, it's perfectly valid to push parts around that aren't perfectly designated yet. I ripped a P2D2 design apart to form the layout for the P2QT and then I deleted the stuff I didn't need. Many times I will start a design simply by looking at form and placement, then I will draw up a schematic, update the parts, change the design, update the schematic, update the pcb etc.
  • It's too early to tell whether the P2 will be a success or not. The same is true for the various P2 PCBs that will be developed. The customers will determine that.

    Please forget the 0.3" layout. That was a joke. It was in response to the statement that 0.6" is impossible. Clearly 0.3" or 0.6" or even 0.1" (DIL) could be done by plugging into adapter boards, or even by adding more layers.

    The 70's DIPs and the solderless breadboards will disappear eventually. Maybe in 5 years. Maybe 10. Or it could be 30 years. Hobbyist still use them, so why not accommodate us instead of telling us we're doing it wrong. Not all of us want to use surface mount parts and reflow ovens and microscopes to see where the solder bridges and gaps are. A lot of us just want to quickly plug things together so we can get to the fun part, which is writing code.

    I'm just trying to express what I would like to see in a P2 PCB. I think other hobbyist would like this also. You can chose to ignore it, and just write it off as those hobbyist just don't know what they're doing.
  • The thread is already hijacked, and no one is interested in this version of my pcb, so please continue.

    Dave,
    As you know, my last comment was to your 0.3” model, which is impossible.

    But since you’re pushing the one you just posted (52x28mm ~2.1x1.1”), which is a looong way from your 0.6” wide (which is too narrow for the P2 chip as I explained above), let’s see you route this keeping correct clearances and decoupling. Peter and I have spent enough time laying out pcbs, including the P2, to know what will fit, what will not fit, and what’s unlikely.

    Peters P2D2 is the closest, and to get the 1.0” pin pitch he’s using 0.050” pins. Using his pcb as the basis, you can only bring out P8-15 + P16-23 on one side, and P40-47 + P48-55 on the other side which is IMHO a useless/weird set of IO. Any other pinout will compromise the width. And 0.1” pins may also be a problem - you see, the 0.1” pads are larger, and the 1.0” pin width (making the pcb 1.1” wide) is a critical minimum. Just ask Peter how much of a problem it was to shrink from about 1.03” to 1.0” it was when I suggested it. Otherwise, something on the pcb has to go.
  • jmgjmg Posts: 14,539
    Dave Hein wrote: »
    I apologize in advance for hijacking Cluso's thread and posting one more 40-pin DIP concept. However, this one has to be doable since it is based on the P2 Edge.
    Yes, Edge is many more than 2 layers - some seem to be assuming the solution must be only 2 layers, yet P2 boards are already 4 and 6 layers.
    via-in-smd also packs things in tighter still, for a small elevation in cost.

  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 19:41:51
    jmg wrote: »
    Dave Hein wrote: »
    I apologize in advance for hijacking Cluso's thread and posting one more 40-pin DIP concept. However, this one has to be doable since it is based on the P2 Edge.
    Yes, Edge is many more than 2 layers - some seem to be assuming the solution must be only 2 layers, yet P2 boards are already 4 and 6 layers.
    via-in-smd also packs things in tighter still, for a small elevation in cost.
    Go for it Jim. Let’s see your design. BTW cost was also a requirement. I’m happy to see your 4 layer, but forget the buried vias.
  • jmgjmg Posts: 14,539
    Cluso99 wrote: »
    ... BTW cost was also a requirement. I’m happy to see your 4 layer, but forget the buried vias.
    This gets funnier :) - more and more 'rules' are being added on here ? - seems 'impossible' was not quite correct then ?
    My issues with DIP form factor, are not around if it is impossible, but I have dismissed it as being 'less practical'. Losing IO pins was the biggest drawback.
  • jmgjmg Posts: 14,539
    Dave Hein wrote: »
    Clearly 0.3" or 0.6" or even 0.1" (DIL) could be done by plugging into adapter boards, or even by adding more layers.
    Yes, I agree.
    Dave Hein wrote: »
    The 70's DIPs and the solderless breadboards will disappear eventually. Maybe in 5 years. Maybe 10. Or it could be 30 years. Hobbyist still use them, so why not accommodate us instead of telling us we're doing it wrong. Not all of us want to use surface mount parts and reflow ovens and microscopes to see where the solder bridges and gaps are. A lot of us just want to quickly plug things together so we can get to the fun part, which is writing code.

    I'm just trying to express what I would like to see in a P2 PCB. I think other hobbyist would like this also. You can chose to ignore it, and just write it off as those hobbyist just don't know what they're doing.
    I can see the area. Is it large enough ?
    Key question here is : Does this need to be 0.6" pin spacing single row, or is 0.1" header good enough ?
  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 20:42:28
    jmg wrote: »
    Cluso99 wrote: »
    ... BTW cost was also a requirement. I’m happy to see your 4 layer, but forget the buried vias.
    This gets funnier :) - more and more 'rules' are being added on here ? - seems 'impossible' was not quite correct then ?
    My issues with DIP form factor, are not around if it is impossible, but I have dismissed it as being 'less practical'. Losing IO pins was the biggest drawback.
    IIRC Dave did state the cost requirement in one of his posts, not necessarily on this thread, or perhaps it was someone else. And if cost isn’t a problem, the you or Dave might like to get dice from OnSemi and make on a ceramic base. After all, the wafer is only about 8.5mm square or about 0.35”.

    My RetroBlade2 is 2.2”x1.6” (1.5” pin pitch) and brings out almost all IO (6 are on larger vias) on 0.1” pins. Peter’s P2D2 is 2.2”x1.1” (1.0” pin pitch) and brings out all IO on 0.050” pins.

    Once you get over the DIP40 obsession, and ditch the stupid 0.6” or 0.9” pin pitch requirement, ether of these two boards should do the job nicely.

    But, repeating it again, let’s see your proper layouts. KiCad is free, so have a go!

    And yes Jim, let’s see you buried via 12 layer 0.6” wide design! I’m really keen to see your design because I’ve not seen one yet.

    Peter and I have taken the time to try and explain why it will not fit the 0.6” or even 0.9” wide requirement. Please, let’s see a design. You don’t have to build it, just show a real kicad design.
  • I think the existence of the P2 Edge is an indication that a board based on it could be routed. The board I show in the file p2dip3.jpg has a 1.1 inch spacing. It would only bring out half of the I/O pins, which would probably be P0-P15 and P32-P47 to make the routing easier. It would have a 4-pin header for the Prop Plug plus the same features as the P2 Edge. It seems like this should be easier to route than the P2 Edge since it's not using 32 of the P2's pins.

    With a 1.1 inch spacing it will plug into a solderless breadboard that has 5 holes on each side with a 0.3 inch spacing in the center. It does require that wires run under the board in the breadboard configuration, but I don't see that as a problem. People could develop their own PCB that accepts the P2 DIP40 with smaller parts mounted below it. It would allow for a compact two-level design.
  • Dave HeinDave Hein Posts: 6,204
    edited 2020-11-02 - 21:30:30
    Downloading KiCad. That thing is huge! It's a 1.2GB download. I wonder how much space it uses on the hard drive. 12 minutes remaining for the download.

    EDIT: Installing now. It says it needs 5.9GB of file space.
  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 21:29:37
    Dave,
    Here is a quick cut/paste of my RetroBlade. Notice that the minimum pin pitch for this design base is 1.04" (1.14" pcb width). However, as the P2 is moved down the pcb in order to give area at the top for the other parts, the pins must move out to accommodate the extra tracks that need to pass to the P2 (the red vertical tracks). So, as the design progresses, the width expands.
    1.04" is the minimum while still retaining proper decoupling, and not resorting to double sided components. Double sided components, or putting the io connections on the reverse side, all cut the ground pad size which is being used as a heatsink too. I have tried to explain this above, obviously without success.
    DIP40test.jpg

    FWIW My design pushes the envelope! The 0603 caps are a smaller footprint than usual, and they are closer to the P2 pads than is usual too. This was all done to save space at the expense of tighter production control. But I refused to compromise with the decoupling layout as that is a performance issue.
    569 x 779 - 233K
  • Dave HeinDave Hein Posts: 6,204
    edited 2020-11-02 - 21:35:13
    I wasn't the one suggesting 0.6 inches. That was someone else. So maybe 1.1 inches is a possibility? How many layers are you doing?
  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 21:41:55
    I don;t think I ever posted this test
    Of course the regs are not routed and the uSD could be swapped out for flash and the uUSB removed. This would give 2x 8 IO ports plus the internal connections for P58-63.
    p2minibladetest.jpg

    But again, as you add IO you increase the width, and the length.

    Or this one with 2x 10 IO. Note how the width expanded for those extra 4 IO.

    P2base003a.jpg
    481 x 533 - 155K
    417 x 543 - 151K
  • Dave Hein wrote: »
    Downloading KiCad. That thing is huge! It's a 1.2GB download. I wonder how much space it uses on the hard drive. 12 minutes remaining for the download.

    EDIT: Installing now. It says it needs 5.9GB of file space.
    Yes, it's huge!

    You will need the P2 footprint. Checkout the P2 KiCad thread where I posted my version.
  • OK, I'll look for it. Is the P2 Edge schematic available? I thought it was, but it looks like it isn't. This is going to take a lot longer if I have to enter the schematic. Fortunately, I don't know what I'm doing, so I haven't given up yet. :)
  • jmgjmg Posts: 14,539
    Dave Hein wrote: »
    I wasn't the one suggesting 0.6 inches. That was someone else. So maybe 1.1 inches is a possibility? How many layers are you doing?

    There are many possible solutions.
    The 0.1" header inner row spacing on P2D2r3 and P2D2Pi is 1.2" , tho if you pick inner row only, the pin map is sparse.
  • Dave Hein wrote: »
    OK, I'll look for it. Is the P2 Edge schematic available? I thought it was, but it looks like it isn't. This is going to take a lot longer if I have to enter the schematic. Fortunately, I don't know what I'm doing, so I haven't given up yet. :)
    I don't think so.
    On the kicad thread I also posted the P2 schematic symbol too.
  • Dave Hein wrote: »
    I wasn't the one suggesting 0.6 inches. That was someone else. So maybe 1.1 inches is a possibility? How many layers are you doing?
    Peter and I are both using 2 layers currently.
  • Dave HeinDave Hein Posts: 6,204
    edited 2020-11-02 - 22:15:49
    jmg wrote: »
    Dave Hein wrote: »
    I wasn't the one suggesting 0.6 inches. That was someone else. So maybe 1.1 inches is a possibility? How many layers are you doing?

    There are many possible solutions.
    The 0.1" header inner row spacing on P2D2r3 and P2D2Pi is 1.2" , tho if you pick inner row only, the pin map is sparse.
    There must be something I'm missing about the 1.1 inch spacing being impossible. I have one of the bare PCBs from Peter's first iteration on the P2D2. I measure 1.06 inches between the 0.05" header rows, and 1.2 inches between the inner 0.1" rows. The P2D2 has a lot more stuff on it than I'm proposing, so I find it a little hard to believe that the board I'm proposing is impossible.
  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 22:24:26
    Dave,
    This is where I got the impression you were wanting 0.6' or 0.9"
    Dave,
    Been thinking some more...
    The RetroBlade is 2.2”x1.6”.
    By reducing the I/O to 32 (P0-15 and P32-47) with 16 + 3V3 and GND gives 18 pins per side or 1.8” down from 2.2”.
    Replacing the microSD with the Flash doesn’t really save any space so the width will need to almost be the same. Perhaps removing the separate 3V3 SOT89 regulator may save 0.2” but there are additional routing issues.
    So perhaps a pcb space might get to 1.8”x1.4”. Even squeezing the width a little further maybe 1.8”x1.2” could be optimistic. It’s certainly not going to be a 2.0”x0.6” (pcb 2.0”x0.7”) or even 2.0”x0.9” (pcb 2.0x1.0”) of the DIP40.

    It would be easier to make a pcb to go underneath a P2D2 or RetroBlade2 to convert to a DIP40, presuming you are trying to plug into a P1 socket.
    and your reply
    Tubular proposed a P2DIL80 that is 1" wide. I believe he presented this in one of the Zoom meetings. It looks like the outer rows of pins are 0.9" apart, and the inner rows are 0.7". Of course, this is just a concept, and I don't know how feasible it is. The P2 is mounted at 45 degrees, and there are no pins where the corners of the P2 are by the edge of the PCB. It fits in a DIL 80 socket, but it doesn't have a full set of 80 pins.

    I'm not concerned about fitting into a P1 socket, but it would be a nice feature. I think Tubular's design has that feature.
    You will note I suggested
    So perhaps a pcb space might get to 1.8”x1.4”. Even squeezing the width a little further maybe 1.8”x1.2” could be optimistic.
    but you didn't indicate that these were acceptable, hence the impression you were sticking to 0.9" or less.

    As I said then, as now, 1.1" pitch is probably the minimum possible while keeping on a 0.1" base. That's a pcb width of 1.2"

    And just so we know what we are comparing, here is from left to right, a P2D2 with the RPi header, the latest P2D2 (top rail needs to be removed - see v-groove cut mark), my RetroBlade2, P2-EVAL Rev A, and on the bottom, a common Arduino clone).

    816C33AD-6214-4EEC-B646-4D0D98C7B255.jpeg
  • jmgjmg Posts: 14,539
    Dave Hein wrote: »
    jmg wrote: »
    Dave Hein wrote: »
    I wasn't the one suggesting 0.6 inches. That was someone else. So maybe 1.1 inches is a possibility? How many layers are you doing?

    There are many possible solutions.
    The 0.1" header inner row spacing on P2D2r3 and P2D2Pi is 1.2" , tho if you pick inner row only, the pin map is sparse.
    There must be something I'm missing about the 1.1 inch spacing being impossible. I have one of the bare PCBs from Peter's first iteration on the P2D2. I measure 1.06 inches between the 0.05" header rows, and 1.2 inches between the inner 0.1" rows. The P2D2 has a lot more stuff on it than I'm proposing, so I find it a little hard to believe that the board I'm proposing is impossible.

    I'm not saying 1.1" is impossible at all, the numbers I quoted were to provide pegs in the sand for existing routed designs.
    If you remove the 50 mil pads option from P2D2, that may be enough to nudge the 1.2" to 1.1"
  • OK, so the part that I was missing was that you were only using 2 layers. I assumed you were using 4 layers. The cost is something like $2.50 versus $5.00 isn't it? I'm pretty sure I read somewhere that the P2 Edge is 4 layers. Maybe with 4 layers the spacing can be less than 1.1", but 1.1" would be OK if it's impossible to make it any smaller.
  • jmgjmg Posts: 14,539
    Dave Hein wrote: »
    .. I'm pretty sure I read somewhere that the P2 Edge is 4 layers. ...
    I thought I saw 6 layers, but I cannot find that comment now ?
    Double sided part placement can also shrink the size.
  • Cluso99Cluso99 Posts: 16,909
    edited 2020-11-02 - 23:38:45
    Dave,
    Now you are up to 1.1" (pin pitch), if it cannot be any less.

    But you're still missing the point. There are minimum widths for the P2 pads. On top of that, with components on one side (assumed) you must have decoupling capacitors outside the P2 footprint. Next you have the traces that go to the IO pins, and lastly the IO pads themselves. I explained that many posts ago, giving you those measurements. They added up to 1.04" as an absolute minimum before other constraints added to that width. Something has to be compromised in order to be able to reduce this minimum. And that minimum doesn't allow for routing.

    Placing the P2 at 45degrees doesn't help if you're wanting to have the 16 IO per pcb side a decent set. Compromising to P8-23 and P40-55 helps the diagonal P2, but placed diagonally is wider than square. I would never compromise my design to just bring out P8-23 rather than P0-15 unless I had a very specific use/target in mind (ie not for general use).

    The pics I posted a few posts back should show you that 1.2" pitch (1.3" pcb) is likely possible, and also show you that 1.1" pitch is quite difficult but maybe just achievable. Every additional IO track that needs to get out and route vertically to it's pad, adds another 0.01" to the width and you need to do this on both sides of the pcb - using 5mil rules and I'm using a little over that.

    My board is 1.6" wide and without much compromise and with 58 IO on 0.1" pins although 2 are on the inner 0.1" header for the similar propplug connection.

    Anyway, I'll wait for you to layout your pcb to see what's possible.

    BTW 4 layers doesn't contribute that much to the minimum width. It's about compromising the design and using 4 layers that would contribute to a narrower design, or by using components on both sides and probably a compromise too.
  • BTW I may have been convinced to try 1 1.2" pin pitch (1.3" pcb width) at the beginning of this thread, but I just don't see the demand.
  • This is what I like about the forum when we can have a spirited discussion and benefit from it because it forces you to think and rethink. It's interesting to note that of the pcbs displayed, that the smaller ones are only 2 layers which are very cheap to make these days, in fact the latest P2D2 pcbs with ENIG cost about 70 cents each. While prices come down with volume, to prototype with more than 2 layers is much more expensive.
  • Peter, it seems like 1.1" row spacing with 0.1" pin spacing could be achieved based on what you've done with the P2D2. I believe your 0.05" pin spacing has 2 rows 1" apart, correct? So how were you able to achieve this when Cluso says it's not possible? Yes, I understand that the solder pads for 0.05" spacing are smaller than for 0.1", but it seems like 1.1" row spacing could be achieved.
  • The 50mil pads are 1" apart so larger 100mil pads could be placed on a 1.1" center easily. The reason the P2 is at an angle is to permit easy access for I/O on a narrow spacing. If you dedicate the top 8 I/O for boot stuff then really you only need to bring out 32 I/O just like the P1. If you have a look at my P2QT you will see it is far easier to mount this tight pcb onto an adapter plate with header pins just the way you like it.
  • The P2 body is 0.55" sq so if I were to reform the pins to press flat against the body and bend under a bit like a PLCC pack, then it might be possible to make a standard DIP40 version. I've got some old Rev A chips I can try this technique on. It's an idea.
  • Dave HeinDave Hein Posts: 6,204
    edited 2020-11-03 - 02:19:34
    OK, I'll take a look at the P2QT.

    EDIT: It looks like the rows are 0.85" apart, which is less than 1.1". However, it's not a DIP, and the pin spacing is 0.05".
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