Propeller-2 Smart-Pin pulse/cycle output (%00100)

See my code below. I can see the generated pulses on my scope.

1. On the Propeller-2 DEV Board I calculate a period of 40 nsec per count in the Smart-Pin pulse/cycle mode. That equals a 25 MHz clock. Is that correct?

2. In this mode, what role does the Y register play? Notes in the V33 docs indicate when it is nonzero, pulses start to appear. Is the Y register a counter that gets decremented at each clock cycle (25 MHz)? Or does the register count the times the X[15:0] count reaches zero? Or does it count something else? Maybe it is not a counter at all and must be set or reset by software. I need an explanation of how to use the Y register to control the number of pulses created in this mode.

3. Does this mode alter any flags? If so, which ones and how? I appreciate the help Forum members have offered to improve the assembly-language documentation. Thank you. --Jon
CON           
    
dat
	org	0         
       dirl     #20			'Setup Smart-Pin at P20
       wrpin    PulseConfig,    #20	'Set configuration for pulse/cycle
       wxpin    PulseTiming,    #20	'Set overall cycle time and logic-0 period
       dirh     #20

       wypin	Cycles,      	#20	'Send count to Y register
		nop			'Delay two clocks for IN to drop

.myloop				
	jmp	#.myloop		'wait here

PulseConfig	long	%0000_0000_000_00000_00000000_11_00100_0     'Pulse/cycle output
                     
Cycles		long	$3A98		'No idea how this value gets used               
PulseTiming	long 	$01F4_05DC	'40 usec logic-1, 20 usec logic-0

Comments

  • evanhevanh Posts: 9,502
    edited 2020-05-17 - 00:05:07
    For this smartpin mode, Y is number of pulses you want to output. Yes, it'll decrement to zero.

    To get an accurate pulse rate you need to set a known sysclock frequency first, eg: For 80 MHz
    con
    	XTALFREQ	= 20_000_000				'PLL stage 0: crystal frequency
    	XDIV		= 20					'PLL stage 1: crystal divider (1..64)
    	XMUL		= 80					'PLL stage 2: crystal / div * mul (1..1024)
    	XDIVP		= 1					'PLL stage 3: crystal / div * mul / divp (1,2,4,6..30)
    
    ' Clock modes: %0000_000e_dddddd_mmmmmmmmmm_pppp_cc_ss
    	XOSC		= %10				' OSC    ' %00=OFF, %01=OSC, %10=15pF, %11=30pF
    	XSEL		= %11				' XI+PLL ' %00=rcfast(20+MHz), %01=rcslow(~20KHz), %10=XI(5ms), %11=XI+PLL(10ms)
    	XPPPP		= ((XDIVP>>1) + 15) & $F	' 1->15, 2->0, 4->1, 6->2...30->14
    	CLOCKFREQ	= round(float(XTALFREQ) / float(XDIV) * float(XMUL) / float(XDIVP))
    	CLK_MODE	= 1<<24 | (XDIV-1)<<18 | (XMUL-1)<<8 | XPPPP<<4 | XOSC<<2
    
    
    dat		org
    
    'Use accurate crystal oscillator and PLL instead of RCFAST
    		hubset	#$f0			'Safe RCFAST
    		hubset	##CLK_MODE		'Power up external 20 MHz crystal and PLL
    		waitx	##25_000_000/100	'10 ms pause for stablising
    		hubset	##CLK_MODE | XSEL	'switch over to PLL as system clock source
    		...
    


    For readability, I'd use decimal entry to fill "PulseTiming", eg:
    PulseTiming	long 	 4800 | 1600<<16	'40 usec logic-1, 20 usec logic-0
    
  • Oh, you can have multiple CON sections, splitting them up and putting the untidy parts at the end of the source code if you want. Eg:
    con
    	XTALFREQ	= 20_000_000				'PLL stage 0: crystal frequency
    	XDIV		= 20					'PLL stage 1: crystal divider (1..64)
    	XMUL		= 80					'PLL stage 2: crystal / div * mul (1..1024)
    	XDIVP		= 1					'PLL stage 3: crystal / div * mul / divp (1,2,4,6..30)
    
    
    dat		org
    
    'Use accurate crystal oscillator and PLL instead of RCFAST
    		hubset	#$f0			'Safe RCFAST
    		hubset	##CLK_MODE		'Power up external 20 MHz crystal and PLL
    		waitx	##25_000_000/100	'10 ms pause for stablising
    		hubset	##CLK_MODE | XSEL	'switch over to PLL as system clock source
    
    'Set up smartpin pulse out mode at pin P20
    		dirl	#20
    		wrpin	#SPM_PULSES, #20
    		wxpin	PLSperiod, #20
    		dirh    #20
    
    'Output number of pulses
    		wypin	PLSpulses, #20
    
    'Twiddle thumbs while smartpin does job
    .pause		waitx	#500
    		jmp	#.pause
    
    
    
    PLSpulses	long	8			'Number of pulses to output
    PLSperiod 	long	4800 | 1600<<16		'Sysclocks per pulse, and sysclocks of duty low time
    
    
    
    con
    ' Clock modes: %0000_000e_dddddd_mmmmmmmmmm_pppp_cc_ss
    	XOSC		= %10				' OSC    ' %00=OFF, %01=OSC, %10=15pF, %11=30pF
    	XSEL		= %11				' XI+PLL ' %00=rcfast(20+MHz), %01=rcslow(~20KHz), %10=XI(5ms), %11=XI+PLL(10ms)
    	XPPPP		= ((XDIVP>>1) + 15) & $F	' 1->15, 2->0, 4->1, 6->2...30->14
    	CLOCKFREQ	= round(float(XTALFREQ) / float(XDIV) * float(XMUL) / float(XDIVP))
    	CLK_MODE	= 1<<24 | (XDIV-1)<<18 | (XMUL-1)<<8 | XPPPP<<4 | XOSC<<2
    
    
    	SP_OUT		= (%1 << 6)			' enable digital output when DIR operates smartpin
    	SPM_NCO_FREQ	= %00110_0 |SP_OUT		' NCO frequency, X[15:0] = base period, Z += Y, OUT = Z[31]
    	SPM_PULSES	= %00100_0 |SP_OUT |(1<<7)		' pulse/cycle output, X[31:16] = base period, X[15:0] = duty of period
    
  • Thanks for that useful and helpful information.

    How do I set the Smart-Pin in pulse/cycle mode so the pulses are inverted? That is, standby output of logic-1 then logic-0 pulses, then back to logic-1 in standby state?
    I have tried to use the letter "O" bit (bit P6 in the Mode-register data), but that causes the following, that you can see in one of the attached images:
    Logic-0 on scope. Then output rises to logic 1 and logic-0 pulses appear. At end of pulse cycle, output remains at logic-1.

    When I run the program a second, third, etc., time without changes, I see the second image--looks like an R-C discharge--from the Smart-Pin connection. So, what's going on? I still need inverted pulses. Thanks--Jon
    CON           
        
    dat
    	org	0         
           dirl     #20			'Setup Smart-Pin at P20
           wrpin    PulseConfig,    #20	'Set configuration for pulse/cycle
           wxpin    PulseTiming,    #20	'Set overall cycle time and logic-0 period
           dirh     #20			'Finished setup
    
           wypin	Cycles,      	#20	'Send pulse count to Y register
    		nop			'Delay two clocks for IN to drop
    .wait4flag	testp		#20  WC	'Test carry flag,
    	if_nc	jmp  #.wait4flag	'No flag? Jump...
    	wypin	Cycles2,	#20	'Yes, flag detected, load new count
    .myloop				
    	jmp	#.myloop		'Program waits forever
    
    PulseConfig	long	%0000_0000_000_0000_001000000_11_00100_0     'Pulse/cycle output
                         
    Cycles		long	$0010		'Pulse count of 16               
    PulseTiming	long 	$01F4_05DC	'60 usec pulse, 20 usec logic-0
    Cycles2		long	$03		'Pulse count of 3
    

    800 x 480 - 16K
    800 x 480 - 12K
  • Jon, I don't see this problem when I run your code. I think your scope is triggering when the download process begins with a reset, causing I/O's to float.
  • Could be, Chip. I'll use a separate output pin to trigger the scope trigger and see what happens. How can I write the code to create logic-0-going pulses? Is there a way to invert the output state of the Smart-Pin circuits? Thanks. --Jon
  • JonTitus, first of all use a pullup resistor.
  • Cluso99Cluso99 Posts: 16,193
    edited 2020-05-18 - 03:44:39
    whicker wrote: »
    JonTitus, first of all use a pullup resistor.
    Why?

    @JonTitus
    Just use OUTL #pin and OUTH #pin
    They will make the pin an output at the same time.

    Presume you mean automatically. Sorry cannot help with this.
  • JonTitus wrote: »
    Could be, Chip. I'll use a separate output pin to trigger the scope trigger and see what happens. How can I write the code to create logic-0-going pulses? Is there a way to invert the output state of the Smart-Pin circuits? Thanks. --Jon

    Jon,
    Here's an example on how to invert a output pin.
    Include this config bit with your smart pin config.
    '  %p..p low level pin control
    '  'CIOHHHLLL' O=1 for invert output
    
    	wrpin	##%001000000 << 8,#56	'invert output	
    	drvh	#56			'led on
    
    
  • larryvclarryvc Posts: 26
    edited 2020-05-18 - 05:53:56
    Deleted
  • The only mistake Jon made was setting his scope to low-going trigger. If he'd left it as high-going he wouldn't have got a trace of the reset pin release.
  • larryvclarryvc Posts: 26
    edited 2020-05-18 - 09:39:43
    Annotation%202020-05-18%20012542.png

    The above was obtained with a slight modification to Jon's code. Start with dirh #20 along with having the invert bit in PulseConfig to obtain steady state logic-1 with logic-0 pulses. PulseTiming value changed to match comments. Hope this is what you wanted Jon, I also solved my pulse timing problem by doing this.

    Seems there is a 2.56ms delay before the beginning of the first logic-1 pulse out of the smart pin, is this normal?

    CON
    
    dat
    
        org 0
        dirh	#20                'Setup Smart-Pin at P20
        wrpin	PulseConfig,   #20 'Set configuration for pulse/cycle
        wxpin	PulseTiming,   #20 'Set overall cycle time and logic-0 period
        drvl	#56                'Finished setup ' trigger scope
    
        wypin   Cycles,     #20     'Send pulse count to Y register
        nop                         'Delay two clocks for IN to drop
    .wait4flag  testp       #20 WC  'Test carry flag,
        if_nc   jmp  #.wait4flag    'No flag? Jump...
        wypin   Cycles2,    #20     'Yes, flag detected, load new count
    
    .myloop
        jmp #.myloop                'Program waits forever
    
    PulseConfig long    %0000_0000_000_0000_001000000_11_00100_0    'Pulse/cycle output
    
    PulseTiming long    1500 | 1000<<16    '60 usec pulse, 40usec logic-1, 20 usec logic-0
    'PulseTiming    long    $03E8_05DC     '60 usec pulse, 40usec logic-1, 20 usec logic-0
    
    Cycles      long    16                 'Pulse count of 16
    Cycles2     long    3                  'Pulse count of 3
    
    

    EDIT: Wording
  • @larryvc
    Seems there is a 2.56ms delay before the beginning of the first logic-1 pulse out of the smart pin, is this normal?
    That is caused by you raising dirh before you configure the smartpin.

  • Thank you all for your helpful information. --Jon
  • ozpropdev wrote: »
    @larryvc
    Seems there is a 2.56ms delay before the beginning of the first logic-1 pulse out of the smart pin, is this normal?
    That is caused by you raising dirh before you configure the smartpin.
    Thanks, it was way to late here to test that again.
  • Peter JakackiPeter Jakacki Posts: 9,096
    edited 2020-05-20 - 02:22:50
    If anyone is interested, this is the way I would do it in TAQOZ in one line of code and hit enter.
    48 PIN   12000 6000 HILO   50 LOW   16 PULSES   WAITPIN   3 PULSES   50 HIGH
    

    My clock is 300MHz so 40us= 12000 and I specify P48 as the target smartpin.
    HILO takes high and low count and sets up the Smartpin.
    LOW drives P50 low.
    PULSES writes wypin with that value (just an alias)
    WAITPIN waits for smartpin ack
    (article on my wiki page)

    PULSES.png
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  • Wow, I'll take a look at Tachyon Forth after I figure out a few more Smart-Pin operations. --Jon
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