Propeller Smart-Pin "DAC with PWM Dither"?

JonTitus

I am not sure what the DAC with PWM output should look like in this mode (%00011). How does the PWM affect the voltage or the period? A sample waveform would help show how the PWM affects the output.

The v33 doc for the Propeller 2 notes the following for the section, "DAC 16-bit with PWM Dither":

X[15:0] establishes the sample period in clock cycles. The sample period must be a multiple of 256 (X[7:0]=0), so that an integral number of 256 steps are afforded the PWM, which dithers the DAC between adjacent 8-bit levels. No problem, I can use 4096.

Y[15:0] establishes the DAC output value (voltage?) which gets captured at each sample period and used for its duration. Where does the Y value come from?

On completion of each sample period, Y[15:0] is captured (captured by what?) for the next output value and IN is raised. Therefore, you would coordinate updating Y[15:0] with IN going high. Why would you do this?

PWM dithering will give better dynamic range than pseudo-random dithering, since a maximum of only two transitions (transitions of what, voltage or time?) occur for every 256 clocks. This means, though, that a frequency of Fclock/256 will be present in the output at -48dB. (As seen in a spectrum plot of the signal, i.e. FFT?)

If OUT is high, the ADC will be enabled and RDPIN/RQPIN can be used to retrieve the 16-bit ADC accumulation from the last sample period. This can be used to measure loading on the DAC pin.

During reset (DIR=0), IN is low and Y[15:0] is captured. Help understanding this mode is greatly appreciated. Thank you. --Jon

Rayman

Y is set by WYPIN instruction.
If you are just setting one value, you don't have to monitor IN.
But, if you are trying to do something like play a .wav file, you'd want to update Y every time IN goes high with the next audio sample...

Ariba

There is only an 8-bit DAC on every pin. To get a 16-bit resolution, you can dither the lowest bit digitally before it goes to the DAC. So you get a fraction of the bit step, according to the high/low ratio of the dithering. For sure the usable output rate for the DAC is lower then.
There are two dither methodes: Noise and PWM. PWM gives more exact results, Noise has a higher dither rate.
For PWM dither you should set the sample period to a multiple of 256, otherwise you disturb the PWM dithering, when you write a new value to the DAC.

Andy

Rayman

I'm wondering about that "must" be a multiple of 256 part. I have a feeling it doesn't matter in any practical way...

Ariba

Rayman wrote: »

I'm wondering about that "must" be a multiple of 256 part. I have a feeling it doesn't matter in any practical way...

When I tested the ADC with a 16bit dithered DAC from another pin, I found you get much more stable ADC values with PWM dither and a multiple of 256 sample rate.
The PWM cycle starts new at every write, so if you set the sample rate to 1 and often write a new value, there is additional noise on the DAC output.

Andy

PropGuy2

On a slightly different note on the DAC pins. What would be the highest frequency you could expect on a DAC pin? 1 MHz, 10MHz, 50MHz or maybe 100MHz Square wave or Sine wave, without too much phase shift.- just asking as I have not tried any of this yet.

whicker

@PropGuy2
The DAC is pushing 1080p VGA, 8-bit of course.

AJL

whicker wrote: »

@PropGuy2
The DAC is pushing 1080p VGA, 8-bit of course.

Which is to say, 148.5MHz by the standard.

Tubular

It was looking mighty fine at 210 MHz too - see photos in this post. The pll wobble issue was corrected in version B silicon

https://forums.parallax.com/discussion/comment/1462193/#Comment_1462193

evanh

JonTitus wrote: »

... On completion of each sample period, Y[15:0] is captured (captured by what?) for the next output value and IN is raised. Therefore, you would coordinate updating Y[15:0] with IN going high. Why would you do this?

Captured in this case means copied from Y register to the live dither register - at the sample period completion. Y is treated as a buffer stage, so whatever you place in Y is not acted on until the next sample period.

cgracey

If you select an output value of $0000, the DAC will steadily output $00.

If you select an output value of $0001, the DAC will output $00 for 255 clocks and then $01 for 1 clock, and then repeat.

Wuerfel_21

cgracey wrote: »

If you select an output value of $0000, the DAC will steadily output $00.

If you select an output value of $0001, the DAC will output $00 for 255 clocks and then $01 for 1 clock, and then repeat.

..and what happens with $FF00 and $FF01 ? How is that handled?

evanh

Ha, I think everything from $ff00 and above will be all the same DAC level of $ff. I presume that's why you've asked.

cgracey

evanh wrote: »

Ha, I think everything from $ff00 and above will be all the same DAC level of $ff. I presume that's why you've asked.

That is correct. I'm pretty sure I put some logic in there to prevent it from toggling between 00 and FF.

JonTitus

Thanks for your comments. There is more involved than dithering the LSB. See attached diagram. Say we have a 3-bit DAC with outputs of 0, 1, 2.. 7 volts and we want 2.2V out, so we start with a DAC input of 010. We can dither the LSB with a PWM signal to get close to 2.2V out. But, suppose you want a 3.5-volt signal. Now you have 011 at the DAC, so dithering the LSB with a PWM decreases the signal to somewhere between 3.0 and 2.0 V.
How does the Propeller's Smart Pin overcome this? I can see two ways (there are probably others). First, an adder between the DAC bits and the DAC lets the PWM signal vary the adder's carry input. In the 3.5-volt example, the DAC would "see" values of 011 and 100 in a ratio proportional to the voltage specified for the Y register. We'd need a fast adder circuit! Second, the pin's circuit could hold the DAC value and the DAC value plus 1. Then the PWM could switch between the two values, 011 and 100.

I assume in a Propeller Smart Pin in DAC-PWM dither mode, the 16-bit value determines the number of PWM pulses that will occur to dither a given DAC input. Also assume the "clock cycles" is the same as the MCU clock cycles. Correct? So the chosen voltage remains steady at the pin output for a minimum of 256 clock cycles. This period must be multiples of 256.

Also, I assume Y[15:0] determines the voltage--eight bits for the DAC, and eight bits for the PWM? Maybe Y[15:8] for the DAC and Y[7:0] for the PWM ratio.

To change the voltage output I simply change the Y-register value. Does the DAC output require a filter of some sort to remove switching noise?

evanh noted,

Captured in this case means copied from Y register to the live dither register - at the sample period completion. Y is treated as a buffer stage, so whatever you place in Y is not acted on until the next sample period.

Does this mean the MCU must constantly update the Y register with the same value to maintain a constant voltage output after the 256 PWM clock period ends? Or that you can load the Y register with a new voltage, but it won't take effect until the end of the 256 PWM clock cycles?

Maybe I'm totally mixed up about the PWM operation, so feel free to offer more information and corrections. You will help make the assembly-language documentation better. Thanks. --Jon

evanh

JonTitus wrote: »

Thanks for your comments. There is more involved than dithering the LSB. See attached diagram. ...

Good drawing! I'd not tried to nut it out myself. #2 looks suitable representation.

... Also assume the "clock cycles" is the same as the MCU clock cycles. Correct? So the chosen voltage remains steady at the pin output for a minimum of 256 clock cycles. This period must be multiples of 256.

Yep, clock cycles of the main system oscillator.

I assume Y[15:0] determines the voltage--eight bits for the DAC, and eight bits for the PWM? Maybe Y[15:8] for the DAC and Y[7:0] for the PWM ratio.

Correct.

To change the voltage output I simply change the Y-register value. Does the DAC output require a filter of some sort to remove switching noise?

That depends on the application. Often the amplifier will be slow enough to filter it for you, or the actuator is inherently too slow and does the same naturally.

Does this mean the MCU must constantly update the Y register with the same value to maintain a constant voltage output after the 256 PWM clock period ends? Or that you can load the Y register with a new voltage, but it won't take effect until the end of the 256 PWM clock cycles?

Y is not erased on the copy. The second one is correct.

Wuerfel_21

Does this mean the MCU must constantly update the Y register with the same value to maintain a constant voltage output after the 256 PWM clock period ends? Or that you can load the Y register with a new voltage, but it won't take effect until the end of the 256 PWM clock cycles?

evanh wrote: »

Y is not erased on the copy. The second one is correct.

Also, IIRC it takes effect when the sample period runs out, regardless of what the PWM is doing.

evanh

What Wuerfel is saying there is that the "period" specified in X register is actually independent of the PWM internal cycling. If X is not a multiple of 256 then don't expect good results.

cgracey

In the DAC dither modes, where N is the 16-bit sample, the 8-bit DAC output alternates between values N>>8 and N>>8+1. In the case of N being $7F80, the DAC would alternate between $7F and $80. So, in half the cases, more than just the LSB is toggling.

evanh

Jon,
Here's the document type write up of PAD_IO_Modes sheet - https://forums.parallax.com/discussion/comment/1452036/#Comment_1452036

And the block diagram and schematics I mentioned - https://forums.parallax.com/discussion/171420/smartpin-diagram/p1
https://forums.parallax.com/discussion/comment/1495181/#Comment_1495181
https://forums.parallax.com/discussion/comment/1495168/#Comment_1495168

JonTitus

Chip: Right, that's why I made a point in my revisions to note the PWM bit gets added to the DAC value. It is not used to simply "wiggle" the DAC's LSB, although some people explain it that way.

Evanh: Thanks for the additional info and links. You are always very helpful. --Jon