Propeller 2 Documentation editing, ver 1.

JonTitus

Here's the editing I have done for the first few paragraphs in the Smart-Pins section. Is this on the right track for what the document for the Prop-2 should look and read like? I think it improves on the basic work and might make things clearer and easier to understand. Feel free to make changes, corrections, or improvements. The attached file is in RTF format. And here is the text without much formatting.--Jon p.s., Parallax people, you might explore a trademark for "Smart Pins."

SMART PINS

Each of the Propeller-2's 64 I/O pins can operate as a standard digital input-output, or it can operate as a Smart Pin. In brief, every Smart Pin provides access to internal functions such as an analog-to-digital converter, digital-to-analog converter, signal generator, PWM controller, and so on. The Propeller architecture lets these functions operate independent of the cogs so they don't rely on software "micromanagement" for control and operation. The Smart Pins are much like a Ronco rotisserie, "Set it and forget it."

The block diagram below shows the main functions for each pair of I/O pins. At first this information will seem complicated, but explanations of the functions, registers, and op codes will clarify and explain how to use Smart Pins.

//Block diagram here...

Each pin has a unique physical pin number, 0, 1, 2... ...62, 63, and pins are grouped in pairs. (The same groupings appear on the Propeller-2 IC package.) A group comprises an even-numbered pin, and an odd-numbered pin, for example, pins 2 and 3, or pins 22 and 23. You cannot have a group with pin numbers 19 and 20. The odd number is always one greater than the even number.

Within each pair, the even-numbered pin is named A and the odd number pin is named B. You can see these letters on signal lines toward the left side of the diagram above.

Smart Pin Registers

Every Smart-Pin circuit includes four 32-bit registers, Mode, X, Y, and Z that control operations:

Register Operation
Mode Controls Smart-Pin modes, as well as low-level I/O (write-only)
X Sets parameters for a specific mode (write-only)
Y Sets parameters for a specific mode (write-only)
Z Information to a cog from a configured pin (read-only)

Programs read and write 32-bit values to and from these four registers following completion of the 2-clock instructions shown here:

WRPIN D/#,S/# - Set smart pin S/# mode to D/#, ack pin
WXPIN D/#,S/# - Set smart pin S/# parameter X to D/#, ack pin
WYPIN D/#,S/# - Set smart pin S/# parameter Y to D/#, ack pin
RDPIN D,S/# {WC} - Get smart pin S/# result Z into D, flag into C, ack pin
RQPIN D,S/# {WC} - Get smart pin S/# result Z into D, flag into C, don't ack
AKPIN S/# - Acknowledge pin S/#

Note:
S/# signifies a literal pin number (0..63) or a symbol, (LED_pin) defined earlier.
D/# signified a 32-bit value to or from a pin register.
{WC} indicates the operation writes to the carry flag? bit?

Each cog shares a 34-bit bus with every Smart Pin and every cog. Data is OR'ed in the same way DIR and OUT bits are OR'd before going to I/O pins. If you intend to have more than one cog access the same Smart Pin with any of these instructions--WRPIN, WXPIN, WYPIN, RDPIN, and AKPIN beware! You must ensure the cogs do so at different times. If the cogs try at the same time they clobber each other's bus data.

Any number of cogs can use an RQPIN (read quiet) instruction simultaneously to read a Smart Pin's data without bus conflict. This instruction does not use the 34-bit cog-to-smart-pin bus for acknowledgement signals. The RDPIN instruction does.

Each smart pin has an outgoing 33-bit bus which conveys its Z result and a special flag. RDPIN and RQPIN are used to
multiplex and read these buses, so that a pin's Z result is read into D and its special flag can be read into C. C will be either a
mode-related flag or the MSB of the Z result.

WRPIN

The WRPIN instruction writes 32-bit data, D/#, to the Mode register for I/O pin identified by the S/# value or symbol. Note: The S/# value only needs to identify the even-numbered pin of the pair. The WRPIN instruction sets the individual mode for the even- and odd-numbered pins in a pair. The following tables describe how the D/# operand controls a pair of Smart Pins:

D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

AAAA Pin A (even-numbered pin) input selector, 4 bits
0xxx = true (default)
1xxx = inverted
x000 = read this pin's state (default)
x001 = read state of pin at this pin's number plus 1
x010 = read state of pin at this pin's number plus 2
x011 = read state of pin at this pin's number plus 3
x100 = read this pin's OUT bit from cogs
x101 = read state of pin at this pin's number minus 1
x110 = read state of pin at this pin's number minus 1
x111 = read state of pin at this pin's number minus 1

Example for A = pin 6 and B = pin 7: If you set AAAA to 1010 you could read the state of the signal at pin 8, (6 + 2). Correct?

JRoark

Ronco. (-snort!-)

pmrobert

Very cool! I seem to recall that the ADCs and DACs are not part of the smartpins but very easily could be wrong.

Tubular

Nice work

@pmrobert the smart pin is effectively distributed between synthesized logic in amongst the cogs, and the 'pad driver' which contains the ADC and several DACs and driving circuits out at every physical pin pad

evanh

I view the smartpins as little processors that are only associated with, rather than encompassing the pin.

AJL

@JonTitus

There seems to be a confusion around the use of A & B of a pin pair in the custom I/O Pad Ring portion of the block diagram and the A & B input selector fields of a WRPIN operand.
In the Pad Ring Pin A is the pin in question, and Pin B is its partner. So, for Pin 0: Pin A is physical pin 0 and Pin B is Physical pin 1, while for Pin 1 these are reversed.

The only function that links a pin pair to be driven only from the even pin is USB.

Otherwise, WRPIN is used on odd pins as well as even pins, and for a given pin the A field selects the primary input, the B field selects the secondary input, and the F filed selects logic and filtering. Each of these can be offset from the actual pin number and is selected in the Logic Input Block. This has been used to allow Smart Pin cells 0 & 1 to snoop on the serial communications happening on Pins 62 & 63 without requiring external wire loops.

The custom I/O Pad Ring functions can be used independently of the Smart Pin functions, but WRPIN configures both.

cgracey

Jon, thanks for writing that. I will review it tomorrow and implement it. Seairth might get to it, as well.

evanh

JonTitus wrote: »

Within each pair, the even-numbered pin is named A and the odd number pin is named B. You can see these letters on signal lines toward the left side of the diagram above.

Oh, yeah, that's wrong. Err, I should have said you've misunderstood ... There is Even/Odd and PinA/PinB naming. They're both needed because the pin/smartpin documenting is generic for all 64 I/O pins. ie: PinA is "this" pin, PinB is its paired pin. Whereas Even and Odd refer to the specific differences within the pair.

EDIT: And as AJL indicated, The %AAAA and %BBBB input selectors is a different stage again. The A/B naming there is in referrence to the smartpins. Each smartpin processor has two inputs, named A and B. A and B each can take input from one of eight sources.

PS: There probably should be some detail about the package pin numbers verses P## pin numbers too. ie: The package pin 1 is the TEST pin, pin 2 is a VDD power pin, pin 3 is the first I/O pin P0, pin 4 is I/O pin P1, pin 5 is a VIO power pin, and on it goes up to package pin 99 being P63 and the final pin 100 is the RESET pin.

evanh

Maybe renaming one of the uses of A/B would be in order. I can see this being a recurring issue.

JonTitus

Here's where I am...
1. We have physical, metal pins, numbered 1 through 100.
2. The I/O pins have a separate designation that we in our code: 40 for P40 (metal pin 65) and41 for P41 (metal pin 66), for example.
3. Again referring to the block diagram, it shows "Physical Even # Pin" and "Physical Odd # Pin." I assume these pin numbers refers to , say P20, P45, and others, but not to the metal pin numbers. Is that correct?
4. Are the even and odd pin numbers contiguous--P20 and P21, or can they be any even and any odd, say P20 and P39.
5. Does each pin have its own "Custom I/O Pad Ring" built in? It seems as though it does, again based on the diagram.
6. Does each pin have Synthesized Core Logic, or is this logic created or connected only when a pin needs it?

Sorry to bother everyone with basic questions.

Also, I think people will have difficulty with the A and B sections shown in the diagram, and the PINA, PINB, OUTA, OUTB... instructions. It can get confusing now that I/O pins have A and B sections.

Thank you all. --Jon

Rayman

2. Yes.
3. Yes.
4. contiguous.
5. There is one custom i/o pad ring around the core that contains all the low level pin drive.
6. There is one core that contains the core logic.

I imagine the core having cog and hub in the middle with pin logic on the outside and then the custom ring around all that...

Rayman

There are some images of the layout here:

https://forums.parallax.com/discussion/168129/full-chip-integration-at-on-semi/p7

So, I guess in reality cog and hub logic are in the middle, then cog ram, then hub ram, then the custom I/O ring...

Ariba

5. Each Pin has it's own Analog circuit (ADC, DAC, Comarator, I/O-Driver). All these analog circuits are arranged as a ring around the chip.

6. Each Pin has it's own smartpin processing unit. This processing logic is normally connected to the related analog pin circuit, but there are some interconnections to ambient pins (-3..+3), so the smartpin logic can also be configured to work with other than the related pin.

Andy

Rayman

There is another map of the core synthesis somewhere here that shows how the cogs are arranged.
I remember it as like a pinwheel with each taking up around a 45 degree sector...

Tubular

Yeah I remember that too but I'm pretty sure it was for P2-hot

There was also some kind of 'blob' image for the newer P2 synthesis, but without the color coding per cog

evanh

"Custom I/O Pad Ring" is referring to custom designed circuits, literally in a ring around the outer border area of the whole die. It goes all the way around. It contains the bonding pads from the silicon die to the metal pins of the package. All pins are connected to the the pad ring, even the core's power and ground have to pass through the pad ring first.

The core logic, or synthesised core logic, is everything that is not in the pad ring, located in the inner die area. It's something like 80% of the total die area.

The block diagram that Rayman and I have worked on, for the 64 I/O pin, shows the functional dividing line as to what is in the outer ring and what is in the inner core area.

evanh

In the custom pad ring, every transistor and track has been mechanically sized and arranged to achieved a desired capability. There was many years involved in just that area before any lines of Verilog were written.

PS: There is a set of disused fuses in there too. Intended to be a unique ID or encryption key. They were abandoned after some testing showed they couldn't be relied upon.

evanh

Here's the floor plan of the I/O pad ring that Chip posted way back. The cyan coloured squares are the bonding pads. Should be 132 in total.

evanh

The clock gen circuitry, which is also part of the custom design, is in the bottom-right corner.

JonTitus

Excellent information. Thanks! --Jon

JonTitus

Making progress re Smart Pins. Just to check:

1. Each Smart Pin has its own logic, ADC, DAC, I/O control... in the Custom I/O Pad Ring. This applies to even and odd pins alike.

2. Within a pin pair, say P20 and P21, software can configure the Custom I/O Pad Ring logic for P20 so it can get the digital state of its paired pin, P21. Likewise, software could configure the custom logic for P21 so it can get the logic state on the P20 pin.

3. There are a few differences between a pair of pins in the Synthesized Core Logic. The even pin's synthesized logic has a RND input to the corresponding orange Logic Output block. The odd pin's synthesized Core Logic received the Output signal from the even pin's Logic Output block. What does this do for us?

4. What is the RND, a single signal or a bus? What does it do? The op-code list and docs do not explain it

5. Suppose I want to set up six pins, P2:P7, as DAC outputs. I use the WRPIN instruction with the D/# information that configures the proper DAC operation. The S/# information for WRPIN identifies one pin, as per the op-code table, S(5:0). Do I need six of the WRPIN instructions with the same mode information, along with unique pin values, 2, 3...7? (Or perhaps a loop?)

6. In one of Chip's examples he includes the line:

wrpin	pm,#7<<6 + 0  	'set triangle pwm mode in smart pins 0..7
pm           %1_01000_0

I don't understand how the single WRPIN instruction sets eight pins simultaneously. The

pm

data is OK. I assumed I would set one pin at a time with its own WRPIN instruction. Maybe I don't understand the

#7<<6 + 0

data and how it affects the operation. Any ideas?

Thanks for your continuing help. --Jon

Rayman

That last thing is a way to affect multiple pins with one instruction... see the spreadsheet for more...

Roy Eltham

JonTitus,
For instructions that take a pin number (like wrpin) the S portion is denoted as this: S[10:6]+S[5:0]..S[5:0] and that means use bits 0 to 5 of the S portion as the starting pin number, then use bits 6 to 10 to add more pins.
What that means is that you can just specify a single pin (e.g. WRPIN pm, #5 means pin P5), or you can specify a range of pins as Chip did with "#7<<6 + 0". What Chip's line does it put a 7 in the [10:6] portion of S, and put a 0 in the [5:0] portion. That means start at pin 0 and add 7 more pins, so it will apply to pins P0 through P7.

JonTitus

The spreadsheet did not illuminate this operation. In C it would read as "add 0 to 6 to get 6, then shift the value 7 (0111) six positions to the left." But the Prop-2 field for pin numbers uses bits 5:0, according to op-code info.

JonTitus

Thanks, Roy. Just the info I need. The spreadsheet data I have shows only:
Write D to mode register of smart pin S[5:0], acknowledge smart pin.
for the WRPIN instruction. I hope the person who keeps this information up to date will add your description. Now I understand how to set a range of pins.
It would help to have name, date, and version (current ver and previous ver) fields in the op-code spreadsheet so we'd know when it got updated and by whom. Cheers. --Jon

evanh

RND is a single bit line straight from the free running random number generator in the hub. Each even numbered pin gets a different bit of the generator. This is then selectable as the logic output, or as bitDAC output, with certain %TT combinations in WRPIN config.

Ariba

> 3. What does this do for us?
The odd/even pair can build a differential output. The odd pin outputs then the complement state of the even pin.

> 4. What does it do?
You can output a random signal at a pin without any software loop. I think Chip just tried to find a good use for the free 'other'-input on even pins, and the random signal was already available (because it's used for DAC dithering)

JonTitus

Thanks.

Cluso99

Roy Eltham wrote: »

JonTitus,
For instructions that take a pin number (like wrpin) the S portion is denoted as this: S[10:6]+S[5:0]..S[5:0] and that means use bits 0 to 5 of the S portion as the starting pin number, then use bits 6 to 10 to add more pins.
What that means is that you can just specify a single pin (e.g. WRPIN pm, #5 means pin P5), or you can specify a range of pins as Chip did with "#7<<6 + 0". What Chip's line does it put a 7 in the [10:6] portion of S, and put a 0 in the [5:0] portion. That means start at pin 0 and add 7 more pins, so it will apply to pins P0 through P7.

IIRC there is also a limitation that it cannot cross a 32 pin boundary. ie a range is limited to pins 0-31 or 32-63. Not sure if it will wrap (ie p28 for 8 pins will give p28-31+P0-3 ???)

Cluso99

2. Within a pin pair, say P20 and P21, software can configure the Custom I/O Pad Ring logic for P20 so it can get the digital state of its paired pin, P21. Likewise, software could configure the custom logic for P21 so it can get the logic state on the P20 pin.

If you look at the most recent Smartpin diagram, there is a block "Logic Input (%A_B_F)". The digital inputs can come from the current pin or any pin +/- 3.

So with P20, you can actually get one of P 17/18/19/20/21/22/23. Neat ay! So you can snoop other pins! IIRC even if they are output(s) from other cog(s).
There is no 32 pin group wrap here.

BTW Chip uses the Smartpins in the boot rom to snoop P63 using P0 & P1 for autobaud detection.

	rx_pin		=	63		'pin serial receiver
	tx_pin		=	62		'pin serial transmitter
	rx_ths		=	1		'pin autobaud time high states
	rx_tne		=	0		'pin autobaud time negative edges