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high gain ADC modes



  • cgraceycgracey Posts: 13,588
    edited 2020-11-21 05:35
    I got away with using thin-ox 1.8V NMOS FETs, which switch twice as hard as the 3.3V NMOS FETs, for way better performance. This was possible because the drain and source voltages on those 1.8V NMOS FETs never get greater than +/-1.8V. And if they do, it's only due to ADC-off-state voltage from parasitic charges, which slowly leak through them, never harming those tiny NMOS FETs.
  • evanhevanh Posts: 10,948
    Oh, are those names like "nmos1p8v" and "rppolyhr", are they from an OnSemi supplied toolkit of some sort?

  • cgraceycgracey Posts: 13,588
    evanh wrote: »
    Oh, are those names like "nmos1p8v" and "rppolyhr", are they from an OnSemi supplied toolkit of some sort?

  • eppolyhr refers to the resistors. Are the tempos of those well matched for the ratios throughout the design?

    Still wondering about block “B”. The ultimate output at BAL has to be a current into the summing capacitors. INFB is a current. So overall current in at INFB becomes a proportional current out at BAL. All set by poly resistors. I’m thinking “B” is a current in to current out, fancy current mirror.

  • evanhevanh Posts: 10,948
    edited 2020-11-21 22:03
    I feel the resistors are well matched. My test comparing GIO/VIO against low/high driven input shows very little difference for the most part. And given the readings are purely Sinc2 filtered, no better quality filter used, probably the noise limit is the biggest factor in my graph -

    EDIT: Okay, I might need to try to apply a better filter. The huge pin to pin differences swamped the visuals. My mentioned 5% is actually 268 mV at roughly 6710 per mV. So an example bad case difference on say P19 for GIO vs driven low is 6164480 - 6076829 = 87651 makes it 13 mV. Much more than I expected.
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