Attenuating ADC input

SaucySoliton

I have a P1 design for measuring +/- 400v. I used the application note for a lot of design help. I added a triangular window filter. It works very well. Maybe I got lucky with opposing tolerances cancelling. Also, I use two of these inputs to measure differential voltage. That may cancel some errors as well.

                       .
     32.4k      2.49M  .2.49M  2.49M  2.49M  
fb----[R]----o---[R]-----[R]----[R]----[R]---- HV in
             |         .
in-----------o------|  .
             |      |  .
            [C]    [C] .
             |      |  .
            GND    VCC .

The output resistance of a P1 pin is about 30 Ohms. So, any slight variation in pin output resistance is insignificant compared to the 32.4k feedback resistor. The whole setup has an input impedance close to 10M Ohms. Resistors have a voltage limit, so 4 resistors are used in series to limit the voltage on any single resistor.

On the P2, the circuitry on the left side of the dotted line is internal to the chip. What tolerance can we expect from these resistors? I assume the P2 adc is intended to be calibrated against VIO and GIO. But I think that only calibrates the ratio of resistors, and the input resistor can still affect the measurements when used with a voltage divider (or high impedance source.)

Or, would it be best to use external components like with the P1?

I would prefer to not need calibration. Voltage references and resistors can be purchased with the desired tolerance. Adding another resistor for a few cents to avoid calibration would be a huge win.

jmg

SaucySoliton wrote: »

On the P2, the circuitry on the left side of the dotted line is internal to the chip. What tolerance can we expect from these resistors? I assume the P2 adc is intended to be calibrated against VIO and GIO. But I think that only calibrates the ratio of resistors, and the input resistor can still affect the measurements when used with a voltage divider (or high impedance source.)

Or, would it be best to use external components like with the P1?

I would prefer to not need calibration. Voltage references and resistors can be purchased with the desired tolerance. Adding another resistor for a few cents to avoid calibration would be a huge win.

External components would certainly be more accurate, and have less tempco and long term drift.

Poly resistors are poor absolute tolerance ( ~20% iirc?), and they also drift with temperature.

It looks like 2M+ resistors can come in 1% and ±50ppm/°C at quite low costs (sub 1c), and ±0.5% ±25ppm/°C pushes up the price to ~ 5c/5k
and you can buy 3 MOhms ±0.1% ±15ppm/°C, but at that spec point, you have to really want them at $9.06/100

ManAtWork

I'd use a resistor devider with lower impedance, say, 4 resistors of 100k in series and 3.3k to ground. That would draw 1mA at 400V and dissipate 0.1W heat at each 100k resistor. I don't remeber the exact numbers but let's assume the P2 ADC has 300k input resistance with +/-20% tolerance.

The 3.3k:300K ratio of divider vs. input resistance reduces the influence of the tolerance of the internal resistor from 20% to about 0.2%. So with 1% tolerance of the external resistors you can get close to 2% worst case accuracy. If you need better accuracy you have to use more expensive components or use manual tuning/calibration.

Edit: I just overlooked that you need +/-400V. So you need a network like this:

                100k   100k   100k   100k  
adc----------o---[R]-----[R]----[R]----[R]---- HV in
             |         
             o------|  
             |      |  
            [R]    [R] 2 x 3.3k
             |      |  
            GND    VCC

SaucySoliton

Thanks jmg! I had forgotten about tempco.

The resistors I used are 1%, 100ppm/°C. My desired tolerance is 1%, worst case <2%, and I don't see any benefits to being <0.5%. Somehow my P1 board is at 0.5% without calibration. (Sample size 1 )

I measured the resistance from one adc pin to another. Resistance in Meg-ohms. The natural midpoint voltage is along the left column.

 V	-	-	-	-	-
bias	+	4	5	6	7
1.587	4	.	1.027	1.138	1.124
1.595	5	1.103	.	1.178	1.165
1.573	6	0.997	0.959	.	1.051
1.575	7	1.001	0.965	1.07	.

So I guess the input impedance is about 500k.



Thanks ManAtWork! If I can figure out the smart pin settings for external ADC feedback, I think I will design the PCB for both methods. I did it before with my P1 board. It supports 1 pin and 2 pin ADC modes. I never tested the 1 pin mode...

I think this is worth investigating further. It would be good to know how repeatable ADC measurements are over temperature, between pins, and between parts.

evanh

SaucySoliton wrote: »

If I can figure out the smart pin settings for external ADC feedback, I think I will design the PCB for both methods.

I think it will be possible to have the paired pin output as an inverted feedback of the ADC bitstream ... but that wouldn't interact correctly with the ADC hardware. The ADC internally is actually an intricate balance of current amplifiers, not resistors.

To get what you want I think you'll be leaving the pin as logic input, with feedback on the paired pin, and using just the smartpin bitstream filter. And reintroducing the old prop1 noise levels!

An alternative is an external sigma delta bitstream modulator chip. A nice option available with these is electrical isolation.

evanh

Here's my constant for using in the paired pin's WRPIN to get an inverted feedback on that paired pin, ie: If pin3 is pinA then pin2 is pinB, and vis-versa. They are an odd-even pin pair.

con
	P_NFB_B		= (%0010 << 17)		' negative feedback, inB -> not out

evanh

Huh, I hadn't tested that very well. It's not inverting of itself, so needs another bit set.

This should do it:

con
	P_REGD		= (%1 << 16)		' turn on clocked digital I/O (registered pins)
	P_IINV		= (%1 << 15)		' invert digital input
	P_OINV		= (%1 << 14)		' invert digital output
	P_FB_A		= (%0001 << 17)		' feedback, inA -> out
	P_FB_B		= (%0010 << 17)		' feedback, inB -> out

dat		org
		wrpin	#P_FB_B | P_OINV, #fbpin

evanh

Okay, so doesn't look like that'll work from the internal ADC bitstream. Not that it would've been useful if it did.

So that feedback pin mode doesn't work from the digital "input" that is fed to the F block. It must pick up the pin logic buffer at an earlier point. Which makes the block diagram I did last year more accurate than I thought. https://forums.parallax.com/discussion/comment/1473762/#Comment_1473762