ADC smartpin help needed

2»

Comments

  • You don't need to do it for every sample

    The GIO value will typically be in the range 10-13k for a 16 bit sample
    The VIO value will typically be in the range 53-56k for a 16 bit sample
    This varies from pin to pin, but they are fairly correlated, so if the GIO value is highish (~13k) for a pin, its likely its VIO will also be highish (~56k). This brings up the possibility of just tracking say GIO (or counterintuitively just tracking VIO as its possibly slightly more stable than GIO)
    Temperature can make those values move around a little bit

    What I got in the habit of doing was this sequence GIO - Signal - VIO - Signal - (repeat...)

    Chip's breakthrough getting calibrated results is this post
    http://forums.parallax.com/discussion/comment/1449144/#Comment_1449144

    and if you follow that thread forward it goes into what affects the calibration values (temperature due to self heating at different frequencies, etc)

    Those results were from Rev A silicon glob tops, but I don't think much has changed in that area. Ie the code still work
  • Ok, thanks. Then I think it's genrally a good idea to connect analogue inputs to a pin pair (not only for the capacitive coupling problem of rev B silicon). This way I could calibrate one of them in the background while doing real conversions with the other. Although Chip somewhere mentioned that the pins have thermal settling times in the µs range I think that two adjacent pins should have aproxximately the same temperature if nothing in the neighbourhood drives high currents. So alternating calibration and real measurements every 100 samples or so should be OK.
  • evanh wrote: »
    Huh, you're right, it looks like Chip has one too many bits. The group of 8 zeros should be 7.

    Have a read of my links if you haven't anyway, you should find them helpful - https://forums.parallax.com/discussion/comment/1483529/#Comment_1483529
    You'll see I've divided the %P's up a little more than Chip does.

    That %FFF filter is not for ADC. That's just a really basic three sample unanimous voting deglitcher for digital inputs.

    Doesn't it
    ManAtWork wrote: »
    Ok, thanks. Then I think it's genrally a good idea to connect analogue inputs to a pin pair (not only for the capacitive coupling problem of rev B silicon). This way I could calibrate one of them in the background while doing real conversions with the other. Although Chip somewhere mentioned that the pins have thermal settling times in the µs range I think that two adjacent pins should have aproxximately the same temperature if nothing in the neighbourhood drives high currents. So alternating calibration and real measurements every 100 samples or so should be OK.

    That's a really good idea. Each ADC will have different calibration values, though. This thermal issue subsides after about 10us of the ADC being turned on. So, it's only an initial turn-on issue, not a calibrate versus read-pin issue. Ganging two pins will let you hide the calibration time and keep the sample rate at 100%.

    1) measure P0 sig and P1 gio
    2) measure P0 gio and P1 sig
    3) measure P0 sig and P1 vio
    4) measure P0 vio and P1 sig, loop

    Some tests will need to be done to determine internal settling time when switching between sig, gio, and vio modes. Switching modes produces brief discontinuities which need to be accounted for.
  • For this reason I'd let the mode switching "overlap"

    1. measure P0 sig and P1 gio
    2. measure P0 sig and P1 vio
    3. measure P0 sig and P1 sig (ignore, let it settle)
    4. measure P0 gio and P1 sig (valid)
    5. measure P0 vio and P1 sig

    ... or with even longer settling time if necessary.
  • I like it.

Sign In or Register to comment.