Propeller 2 Update: Engineering Change Order (ECO) for A/D Performance Schedule

Ken GraceyKen Gracey Posts: 6,532
edited 2019-12-04 - 04:55:36 in Propeller 2
Hello Community,

Today, Parallax met with ON Semiconductor to review the improvement Chip requested to the latest silicon. I'd like to bring you current on what this means for Parallax and you, our valued community. The live development of the P2 goes with real transparency, so here it is.

First, a bit of background on the engineering issue. I'm the business guy, so if you want real engineering details you'll need to read the many posts from Chip on the forum or whatever community replies are made below. Shortly after we approved the Revision B silicon for production Chip discovered a performance issue with the A/D where neighboring inputs were causing some capacitive coupling, reducing the resolution of the A/D to something low - like four bits instead of 14 bits. The ways around this were to couple A/D pins together, skip A/D inputs to every other pin (and ground the ones in between), or just accept slow frequency sampling. While these workarounds exist, there's also a special scope mode built into P2 hardware that uses sequential pins to generate signals. Simply cutting a trace or dropping a via on the mask set fixes this issue with 100% certainty. I understood it really well with "imagine being in a library where you were trying to study and somebody was screaming next to you". If you want to focus there's not much you can do except put the screamer in another room with two walls between you.

In today's meeting, we reviewed two courses of action. First, the current course of action called the non-ECO route which involves receiving production volumes of the P2 in April. This schedule has some parallel processes built into it, like some final packaging qualifications being done by ON Semiconductor while we order chips at-risk (read: our risk, like the chips you have, at a significant per-unit cost to Parallax). The ECO route (with the A/D improvement) starts the 22-week countdown for Rev C production parts in April, for an October release but maybe a bit earlier. It also provides us with another at-risk delivery of Rev C chips, potentially in April. ON Semiconductor has had weekly to month project management meetings with us for several years now and looks for parallel efforts whenever possible (their team is superior to all prior efforts I've been in for P2). For example, today we made a good-faith commitment to continue with the ECO and sign contracts as soon as ready. This allowed them to pull a few in-process wafers planned for the packaging qualification and modify them for the A/D trace cut pretty easily.

Bottom line: Rev C P2 silicon nearly certain by April, production parts planned by October 2020. We are proceeding with the ECO. You, Parallax and ON are *all in*. The ECO comes at a significant engineering cost (much more than discussed here) and with a longer timeline and more at-risk purchases. But it's clear: we've got to do this! Simply hearing Chip describe the issue is enough; no marketing hogwash or datasheet nonsense can bury this performance issue.

We will rely heavily on the community to help us bring this to market, as we don't have the resources internally (we're down to a team of 20). Your numerous contributions are more important than ever. Chip is now working to complete Spin2 so a wider number of users can get started. Some of our team was working on P2 projects but I am turning their attention back towards educational customers (teacher workshops, educational support, robotics, software improvements, some new products). Parallax is still making some internal efforts to plan for the P2, like moving OBEX to GitHub and making a complete repository where your work can be hosted, making a simple P2 web site from propeller.parallax.com and keeping the parts moving into your hands. We'll also plan a P2 module when we see that the Rev C silicon is well underway.

Customers should certainly get started with their current P2 chips. They'll run the same code, speed and memory! Believe in what we're doing at Parallax and you'll have production chips by the time you finish your coding and PCB.

Thanks,

Ken Gracey

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Comments

  • Thanks for the update, Ken

    It will be good to have this fixed.
  • I am with you guys to bring the next generation technology to market.
  • jmgjmg Posts: 14,152
    Ken Gracey wrote: »
    Bottom line: Rev C P2 silicon nearly certain by April, production parts planned by October 2020. We are proceeding with the ECO.

    How many April delivery parts ?

  • Tubular wrote: »
    Thanks for the update, Ken

    It will be good to have this fixed.

    Hear Ye, Hear Ye!
    davekorpi1 wrote: »
    I am with you guys to bring the next generation technology to market.

    That's the spirit! Board the spaceship!

    Thanks,

    Ken Gracey
  • jmg wrote: »
    Ken Gracey wrote: »
    Bottom line: Rev C P2 silicon nearly certain by April, production parts planned by October 2020. We are proceeding with the ECO.

    How many April delivery parts ?

    Probably 1K units.

    Ken Gracey
  • I think this is worth it for sure. The A/D stuff is one of the really strong points of the P2, especially that it's every pin.

    Does this mean the expo is delayed also?
  • Roy Eltham wrote: »
    I think this is worth it for sure. The A/D stuff is one of the really strong points of the P2, especially that it's every pin.

    Does this mean the expo is delayed also?

    Yes.

    Ken Gracey
  • Can the change be tested with the Micrion FIB machine?
  • evanhevanh Posts: 8,400
    edited 2019-12-04 - 06:01:29
    Given it's a complete reschedule and whole new round of engineering samples, I feel like we should also be pushing other smaller fixes into this too.

    One in particular would be fixing the PLL clock source select de-glitch circuit.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • cgraceycgracey Posts: 11,954
    edited 2019-12-04 - 06:02:53
    Can the change be tested with the Micrion FIB machine?

    No. We unloaded the FIB machine several years ago. It was expensive to maintain and we were years away from needing it.

    This change is so trivial that it's not even worth trying at any likely expense using existing chips. We need new wafers without the PinB connection into the ADC resistor array. That will solve the problem.

    It just takes more money and time now. It's funny to think how I could have made that edit in one minute back when I was working on the layout, but I had no idea.
  • whickerwhicker Posts: 504
    edited 2019-12-04 - 06:06:47
    I'm deeply concerned. I thought the P2 was a sure thing this year, and for a select few it actually was. What would it take for a real release of let's say 6000 in April?

    Otherwise at 1000 it's just vaporware. We had momentum on those rev B boards, which if allowed to fizzle we're all done here. No variants in the P2 family. What if the 64 i/o chip can only do 32 analog in? Still impressive.

    It's like, the way it was presented, just $5K and a simple low risk change, and still April. And now massive expense and October 2020? Good grief.

    It's like the story where the contact margin bought the work truck, but the change orders bought the yacht and trailer being towed. I think despite how "nice" it's still gouging, like an eccentric millionaire using their life savings to build the "perfect " mansion.
  • whicker wrote: »
    I'm deeply concerned. I thought the P2 was a sure thing this year, and for a select few it actually was. What would it take for a real release of let's say 6000 in April?

    Otherwise at 1000 it's just vaporware. We had momentum on those rev B boards, which if allowed to fizzle we're all done here. No variants in the P2 family. What if the 64 i/o chip can only do 32 analog in? Still impressive.

    It's like, the way it was presented, just $5K and a simple low risk change, and still April. And now massive expense and October 2020? Good grief.

    It's like the story where the contact margin bought the work truck, but the change orders bought the yacht and trailer being towed. I think despite how "nice" it's still gouging, like an eccentric millionaire using their life savings to build the "perfect " mansion.

    It's going to cost $25k to fix this. We can order more parts, but our unit cost is 2x normal pricing.

    If someone wants more chips, we can get them, if we know, but I think it will realistically take people 6 months to a year to have their first products designed, so that they will need any volume.

    In the meantime, we can support development efforts with probably little difference than if we had infinite chips to sell.
  • Cluso99Cluso99 Posts: 15,549
    edited 2019-12-04 - 07:29:03
    Thanks for the update Ken.

    I had thought it was only going to cost around $5K and no delay :(
    But it is what it is.
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
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  • evanh wrote: »
    Given it's a complete reschedule and whole new round of engineering samples, I feel like we should also be pushing other smaller fixes into this too.

    One in particular would be fixing the PLL clock source select de-glitch circuit.

    That would cost a lot to address, like maybe $60k, and it would take extra months. Even adding the guard rings around the offending N-wells would cost $60k.
  • Too bad about the delay but it sounds like the right decision.
  • I think we all need to realize what "Engineering Sample" means.
    Although I want (need) the P2 to be released for business reasons. I fully understand and support this change.
    I have an existing design that uses the P1 and I am making great progress in converting it to the P2 with much better specs.
    I don't know if it is possible, but I would be willing to buy some more of the Rev B chips at the $25 price.

    Bean
  • Seems to me that the 64 ADCs is a distinguishing feature of P2.
    For that reason, it probably makes sense to get it right.

    However, to me, it seems like Parallax went forward too fast with the production order.
    Personally, I would have waited even a bit longer than now for that...
    I just can't believe that everything has been tested yet.
    On the other hand, everything that I care about seems to work...
    Prop Info and Apps: http://www.rayslogic.com/
  • evanhevanh Posts: 8,400
    edited 2019-12-04 - 14:47:53
    The rescheduling hasn't incurred any more cost than it would have if it hadn't been started. It's just an extra round of engineering samples is all. EDIT: ... as far as I can see. :)

    EDIT2: Chip's original hope was to insert the change without any samples being made. On Semi have obviously said a clear no to that idea.

    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • Bean wrote: »
    I think we all need to realize what "Engineering Sample" means.
    Although I want (need) the P2 to be released for business reasons. I fully understand and support this change.
    {...}
    I don't know if it is possible, but I would be willing to buy some more of the Rev B chips at the $25 price.
    Ditto. This.

    If we can continue to get a dribble of P2 Rev B silicon for dev purposes, this delay wont be that painful for me. Product development efforts can continue, and about the time the Rev C chips hit, I’ll be ready for them. And in the meantime, those all-important reference docs can get some attention, and the toolsets can progress further towards maturity.

    IMHO, Parallax is making a tough but correct choice here.
  • Will you be making more P2 Eval boards prior to April when Rev C chips are expected?
  • There will be one more smaller batch in the store about 3-4 weeks from now. Maybe a bit sooner- just waiting on some parts.
  • @VonSzarvas in that case it might be better to change the "product not available" on the 64000-ES to some other message, like "back in stock shortly"

  • Fair observation, Tubular. It is disabled for ordering to prevent it going into back-order for more units than we are building - an unusual precaution since our Rev B ES chip quantities are limited at this point. I have made a note on the product page that a build of 100 units is scheduled for mid to late December, and that ordering will be enabled when they return to stock (though I might re-enable it early when we get close to an in-stock date).
  • Fair observation, Tubular. It is disabled for ordering to prevent it going into back-order for more units than we are building - an unusual precaution since our Rev B ES chip quantities are limited at this point. I have made a note on the product page that a build of 100 units is scheduled for mid to late December, and that ordering will be enabled when they return to stock (though I might re-enable it early when we get close to an in-stock date).
    When these new units become available will it be possible for people who have already purchased a RevB board from the first batch to buy a second board?

  • Yeah that should help Steph
  • I agree, it would be nice to one at work and one at home.

    Bean
  • I'm not sure about buying second boards yet; we'd love to accommodate the requests but we have folks who are waiting to buy first boards still at this point.
  • I'm not sure about buying second boards yet; we'd love to accommodate the requests but we have folks who are waiting to buy first boards still at this point.
    Understood. It's certainly more important to get people their first boards than to get me a second board.

  • I completely trust Chip, Ken, Team Parallax, and the countless volunteers working on the P2!

    Go, go, go! April will be here before you know it.
    Whit+

    "We keep moving forward, opening new doors, and doing new things, because we're curious and curiosity keeps leading us down new paths." - Walt Disney
  • Ken Gracey wrote: »
    ... Chip discovered a performance issue with the A/D where neighboring inputs were causing some capacitive coupling, reducing the resolution of the A/D to something low - like four bits instead of 14 bits. The ways around this were to couple A/D pins together, skip A/D inputs to every other pin (and ground the ones in between), or just accept slow frequency sampling.

    Hello Ken,

    could you please explain theese workarounds a bit more? The coupling is capacitive, so if I understand correctly there is no DC error. And if I have enough spare pins I could ground every second pin between the ADC inputs and the error could be neglected?

    For example, if I drive a motor with a PWM power stage and measure the winding current with hall current sensors and if I sample the analogue voltage over a complete PWM cycle then all capacitively coupled errors should be cancelled out, right?

    I'm currently designing a new product and I have to decide if I give the P2 another chance or not. Waiting until Oct 2020 is a no-go. I can live with some restrictions as long as there are workarounds. But I'd need engineering samples ASAP and at least small production volume (~100 units) the next 1/2 year.

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