Today, Parallax met with ON Semiconductor to review the improvement Chip requested to the latest silicon. I'd like to bring you current on what this means for Parallax and you, our valued community. The live development of the P2 goes with real transparency, so here it is.
First, a bit of background on the engineering issue. I'm the business guy, so if you want real engineering details you'll need to read the many posts from Chip on the forum
or whatever community replies are made below. Shortly after we approved the Revision B silicon for production Chip discovered a performance issue with the A/D where neighboring inputs were causing some capacitive coupling, reducing the resolution of the A/D to something low - like four bits instead of 14 bits. The ways around this were to couple A/D pins together, skip A/D inputs to every other pin (and ground the ones in between), or just accept slow frequency sampling. While these workarounds exist, there's also a special scope mode built into P2 hardware that uses sequential pins to generate signals. Simply cutting a trace or dropping a via on the mask set fixes this issue with 100% certainty. I understood it really well with "imagine being in a library where you were trying to study and somebody was screaming next to you". If you want to focus there's not much you can do except put the screamer in another room with two walls between you.
In today's meeting, we reviewed two courses of action. First, the current course of action called the non-ECO route which involves receiving production volumes of the P2 in April. This schedule has some parallel processes built into it, like some final packaging qualifications being done by ON Semiconductor while we order chips at-risk (read: our
risk, like the chips you have, at a significant per-unit cost to Parallax). The ECO route (with the A/D improvement) starts the 22-week countdown for Rev C production parts in April, for an October release but maybe a bit earlier. It also provides us with another at-risk delivery of Rev C chips, potentially in April. ON Semiconductor has had weekly to month project management meetings with us for several years now and looks for parallel efforts whenever possible (their team is superior to all prior efforts I've been in for P2). For example, today we made a good-faith commitment to continue with the ECO
and sign contracts as soon as ready. This allowed them to pull a few in-process wafers planned for the packaging qualification and modify them for the A/D trace cut pretty easily.
Bottom line: Rev C P2 silicon nearly certain by April, production parts planned by October 2020. We are proceeding with the ECO. You, Parallax and ON are *all in*.
The ECO comes at a significant engineering cost (much more than discussed here) and with a longer timeline and more at-risk purchases. But it's clear: we've got to do this! Simply hearing Chip describe the issue is enough; no marketing hogwash or datasheet nonsense can bury this performance issue.
We will rely heavily on the community to help us bring this to market, as we don't have the resources internally (we're down to a team of 20). Your numerous contributions are more important than ever. Chip is now working to complete Spin2 so a wider number of users can get started. Some of our team was working on P2 projects but I am turning their attention back towards educational customers (teacher workshops, educational support, robotics, software improvements, some new products). Parallax is still making some internal efforts to plan for the P2, like moving OBEX to GitHub and making a complete repository where your work can be hosted, making a simple P2 web site from propeller.parallax.com and keeping the parts moving into your hands. We'll also plan a P2 module when we see that the Rev C silicon is well underway.
Customers should certainly get started with their current P2 chips. They'll run the same code, speed and memory! Believe in what we're doing at Parallax and you'll have production chips by the time you finish your coding and PCB.