Si5351A Clock Generator on P2D2Rn/P2D2Pi/P2D2PiFLiP

A new thread for Si5351A discussions, to avoid clutter of other P2D2 threads.

Parts under test/discussion are
Si5351A-B02075-GT  Crystal Frequency: 27 MHz Internal Load Capacitance (CL): 10pF I2C Address = 0x6F
CLK0 = 24.576 MHz, Reference = Crystal
CLK1 = OFF
CLK2 = OFF

Si5351A-B04486-GT  Crystal Frequency (MHz): 25.000000000 Internal Load Capacitance (pF): 10 Default I2C address: 0x62 
Output Clock Configuration:
CLK0 (MHz): 49.152000000 from PLLA
CLK1 (MHz): 24.000000000 from PLLB
CLK2 (MHz): 45.158400000 from PLLB

Si5351A-B-GT Standard part   Default I2C address: 0x60 

Plus custom codes...
A trap there, is the i2c addresses change !

There are bits to MUX Xtal_XO to CLKn, and a minimal i2c packet should allow a Si5351A to drive Xtal to CLK1

Comments

  • jmgjmg Posts: 14,027
    edited 2019-11-04 - 22:03:35
    Minimal Si5351A-B-GT i2c config tests, from Power up :
    These derived by take a working register set, and throw stuff away until it stops working (& some feedback from SiLabs).
    Turns out you can enable Xtal to Pins with a single i2c register write :)

    Writing 2~5 Registers allows finer control of Xtal C, and Icc can be lowered ~4mA by disable of CLK0, CLK2 pin drives.

    Power Up Icc = 13.73mA (no outputs, reset state)

    1 Line Enables Xtal to CLK0,1,2 at default 2mA drive level and default 10pF Xtal Cap = 24.99977MHz on test board.
    Icc = 15.81mA Scope connected
    Address,Data
    0x00BB,0x40   << added, 187.6 XO_FANOUT_EN  IMPORTANT
    

    2 Lines Enables Xtal to CLK0,1,2 at 2mA drive level, with adjusted (here 8pF) XTAL CAP
    Icc = 14.6mA
    Address,Data
    0x00B7,0x92   7:6 XTAL_CL[1:0]    0x92 => 25.00027MHz (8p)  0xD2 =>  24.99977 (10p)  0x12  => 25.00717
    0x00BB,0x40   << added, 187.6 XO_FANOUT_EN  IMPORTANT
    

    Or, adding 3 more lines can set drive to CLK1 and disable CLK0, CLK2 for lowest Icc of
    Icc = 11.62mA scope probe on, 10.41mA no scope
    Address,Data
    0x0010,0x80  Disable CLK0 driver  CLK0_PDN MS0_INT MS0_SRC CLK0_INV CLK0_SRC[1:0] CLK0_IDRV[1:0]  Reset value = 0000 0000 
    0x0011,0x03    Edit to 0x03 for FORCE Xtal -> CLK1, 8mA,  
    0x0012,0x80  Disable CLK2 driver 
    0x00B7,0x92   7:6 XTAL_CL[1:0]    0x92 => 25.00027MHz (8p)  0xD2 =>  24.99977 (10p) 0x12  => 25.00717
    0x00BB,0x40   << added, 187.6 XO_FANOUT_EN  IMPORTANT
    

    Icc is total power into AdaFruit Si5351A board, (25.00 MHz xtal) so includes regulator Iq of ~ 120uA
  • roglohrogloh Posts: 1,460
    edited 2019-11-05 - 02:20:25
    With the talk of different clock frequencies being used between P2D2 variants and P2-EVAL I wonder if there will be any software considerations to take into account? I know that the PLL/clkmode is intended to be saved into fixed addresses, but what about source crystal/clock frequency on the board. Is that also present and if not is it required?

    I'd try to hunt down through old threads to see where things were left at with the special allotted addresses for these various parameters like clkmode/baudrate, but I'm busy right now and from memory I don't think that the crystal frequency was one of them. Should it be or will it not matter in the end? I'm just thinking of software that may try to make assumptions on the frequencies possible using dynamic clkmode changes after bootup, (which has it's own lockup issues I know, evanh). I guess those cases will need to use a compile time constant with the input oscillator frequency so each object created is customized specifically for the target board...? Are there any cases where the original clock input frequency needs to be known at runtime, to execute shared/network code for example, that was built for a common target whose clock source is not known at compile time.
  • jmgjmg Posts: 14,027
    edited 2019-11-09 - 23:21:53
    rogloh wrote: »
    With the talk of different clock frequencies being used between P2D2 variants and P2-EVAL I wonder if there will be any software considerations to take into account?
    I think 20MHz was chosen simply as a 'nice round number' (It's not USB or Baud related) but 26MHz has a better price curve, as that is widely sourced for GPS uses & Bluetooth.

    ~~~~~~~~~~~~~~~~ 26MHz timebase options ~~~~~~~~~~~~~~~~~~
    These could be used with a full 26MHz -> 20MHz PLL init of Si5351A

    K2C260000910 KYX 26MHz ±10ppm SMD-2520 26MHz ±10ppm 9pF 40Ω ±10ppm -40~85℃ ±3ppm/yr 2996 In stock 500+ $0.0727
    S2226000081060 JGHC SMD 26MHz ±10ppm SMD-2520_4P ±10ppm 8pF 80Ω -10~70℃ 500+ $0.0633
    6250-2600A0910-00 XTY 26MHz ±10ppm SMD-2520 ±10ppm 9pF 60Ω ±20ppm -40~85℃ ±3ppm/yr 500+ $0.0703
    Failong Crystal 3S26000266 SMD-3225-4PAD ±10ppm ±10ppm -20~70°C 9pF 500+ US$0.048


    and 0.5ppm Oscillators show just how much better the prices and stocks are for 26MHz - LCSC shows 28 choices for low ppm 26MHz
    VCTCXO 1XXA26000MAA KDS Daishinku 26MHz ±2ppm SMD-2520_4PAD 2.8V -30~85°C : ±0.5ppm, Vcc/Load :±0.1ppm, max Slope < 0.05ppm/°C -20~65°C VC ±9ppm ±1ppm/yr ±2.5ppm/5yr
    500+ $0.2409 2524 Instock


    ASVTX-13-D-26.000MHz-I05-T ABRACON TCVCXO Oscillators 26MHz 3.3V ±0.5ppm ± 1ppm/year -40~85℃ 2 x 1.6 x 0.8 mm $3.58/1

    TWEAMCSANF-26.000000 Taitien Clipped Sine Wave 3.3V ±100ppb -20~70°C 3.5mA 4-SMD 5.00 x 3.20mm $10.92/100
    XTCLH26M000THJA0P0 Murata VCTCXO 26MHz ±0.2ppm -40~85℃ +3.0±5% (Vcc) ±0.5ppm/year CLSW 8-Pin SMD 5032 $9.38/1+
    LFMCXO075078Bulk IQD VCMCXO 26.0000MHZ HCMOS 3.3V ±50ppp -40~85°C 10mA 8-SMD, 7 x 5 mm $58.85/1+ Voltage con

    SiLabs somewhat artificially limit their SW choices for XIN on Si5351A, which is a bit annoying, however because their family parts use the same register sets, I've dug to find a way to patch a file that was created using CLKIN on larger family members, to use the XIN of the MSOP10.
    Doing that allows 10~40MHz frequency entry choices, and I'm sure the Xtal Osc is fine for 20~27MHz.


    Let's consider some possible options, should P2D2 move to 20MHz Xtal/Osc and uses simple Xtal direct config ? :

    ~~~~~~~~~~~~~~~~ 20MHz timebase options ~~~~~~~~~~~~~~~~~~
    Oscillators:
    From top-end, best ppb, any package
    OCXO have higher stability, but need high Icc for the oven control
    AOCJYR-20.000MHz-M5627LF (Mouser 250 On Order DK 144 ) ABRACON OCXO 20MHz 3.3V -40C +85C +-20 ppb 9.7 x 7.5 x 4.1 mm $44.83/1+
    AOCJYR24.576MHzM6069LF 3.3 Abracon VCOCXO ±50ppb ±2.00ppb/°C -40 to +85°C HCMOS $32.21/1+ Voltage control, but not 20MHz
    OX-6011-EAE-1080-20M000 Microsemi OCXO HCMOS 20MHZ HCMOS 3.3V ±10ppb -40~85°C 4-SMD 9 x 7 x 4.30mm $46.14/1
    AOC1409VAUC-20.0000C 20MHz VCOCXO CMOS Oscillator 3.3V 6-SMD, ±10ppb (APR)±0.7ppm -40°C ~ 85°C 289mA 14.90mm x 9.70mm x 7.00mm $81.670/1+

    AST3TQ-V-20.000MHz-50-C ABRACON VCTCXO Oscillators 20.0MHz LVCMOS ±0.05ppm at -40C +85°C 28 stk Mouser 7 mm x 5 mm $71.85/1+

    DOT050V-020.0M Connor-Winfield VCTCXO 20.0000MHz 93 stk 20MHz LVCMOS 3.3V ±50ppb 0°C ~ 70°C 10mA 6-SMD (13.97 x 9.02 x h6.86mm) $26.95/10


    Newish are MCU assisted oscillators, close to OCXO in specs but lower Icc
    LFMCXO064079BULK IQD VCMCXO 19.2000MHZ HCMOS 3.3V ±50ppb -40~85°C 10mA 8-SMD 7 x 5 mm $58.85/1+ Voltage control, but not 20MHz
    LFMCXO064080BULK IQD VCMCXO 20.0000MHZ HCMOS 3.3V ±50ppp -40~85°C 10mA 8-SMD, 7 x 5 mm $58.85/1+ Voltage control 20MHz, DK,Arrow,Mouser
    MX-600 Microsemi (vc)MCXO HCMOS 12mA 20ppb 9.6 x 7.4 x 4.1 mm prices tbd,


    Narrowing to best-spec found in 5x3.2 package
    AST3TQ53-V-20.000MHZ-5-C Abracon VCTCXO 20.0000MHZ LVCMOS 3.3V ±50ppb -40°C ~ 85°C 6mA 4-SMD (5.00mm x 3.20mm x 2) $84.93/1+

    M100V-020.0M Connor-Winfield VCTCXO 20.0000MHZ LVCMOS 250 stk 3.3V ±100ppb 0°C ~ 70°C 3.3mA 8-SMD (5.00mm x 3.20mm) $24.75/1+

    And there are ±0.2ppm max, in 5032, hence I've expanded OSC footprints in P2D2Pi, to include 5032 to support this

    XTCLH20M000CHJA0P0 20.00MHz VCTCXO CMOS Clipped Sine Wave 3.3V ±0.28ppm -40~85°C 3mA 8-SMD 3.20 x 2.50 x 1.00mm $9.40/1+
    LFTVXO075807REEL IQD 20.000 MHz VCTCXO Clipped Sine Wave 3.3V ±0.28ppm -40~85°C 5mA 4-SMD 3.20 x 2.50 x 1.00mm $11.30/1+

    LFTVXO079052 IQD ±0.5PPM -30~85°C VCTCXO 20MHz 1.8V 1.5mA 4-SMD 2.00mm x 1.60mm $2.78070 @ qty 100

    ASVTX-09-20.000MHZ-T ABRACON TCVCXO Clipped Sine 20MHz 3.0V ±2.5ppm ± 1ppm/1st year -30~75°C 270 stk 4-SMD 5 mm x 3.2 mm $3.80/1+


    KDS Daishinku 1XTV20000CAA is VCTCXO Clipped Sine, 3.3V, ±1ppm -40~85°C ±1ppm/yr for 10+ $0.9030 100+ US$0.7864

    P2 is well suited to such VCTCXO, as they can use a DAC to fine-tune against an external reference, like GPS 1pps.

    ECS-3225S33-200-FN-TR XO 20.0000MHZ HCMOS 1,000 stk ECS-3225S 3.3V ±10ppm -40°C ~ 85°C $0.75520/1k
    Mouser:
    ECS-TXO-2016-33-200-TR TCXO 20MHz 3.3V ±2.5ppm -40~85°C On Order: 1000 1,000 $0.966

    LCSC Xtals:
    XTY 7325-2000A1010-00 20MHz 10pF ±10ppm ±20ppm -40°C ~ 85°C ±3ppm/yr SMD-3225 500+ US$0.0555
    JYXT32S4-020.00000-91C4B0 20MHz 10pF ±10ppm ±20ppm -40°C ~ 85°C ±3ppm/yr SMD-3225 500+ US$0.0703
    DK:
    ECS-200-10-33B-CKM-TR 2,000 stk 20MHz 10pF ±10ppm ±10ppm -20~70°C 40 Ohms $0.28800/1k
    Mouser: (same part, differing reel sizes)
    TSX-3225 20.0000MF20G-AC3 Epson 20MHz 9pF ±10ppm ±20ppm -40~105°C ±1ppm/yr (On Order 14998) 500 $0.192 << this one in Eval RevB
    TSX-3225 20.0000MF20G-AC0 Epson 20MHz 9pF ±10ppm ±20ppm -40~105°C ±1ppm/yr (On Order 1000) 500 $0.193

    rogloh wrote: »
    ... I know that the PLL/clkmode is intended to be saved into fixed addresses, but what about source crystal/clock frequency on the board. Is that also present and if not is it required?

    I'd try to hunt down through old threads to see where things were left at with the special alloted addresses for these various parameters like clkmode/baudrate, but I'm busy right now and from memory I don't think that the crystal frequency was one of them. Should it be or will it not matter in the end? I'm just thinking of software that may try to make assumptions on the frequencies possible using dynamic clkmode changes after bootup, (which has it's own lockup issues I know, evanh). I guess those cases will need to use a compile time constant with the input oscillator frequency so each object created is customized specifically for the target board...? Are there any cases where the original clock input frequency needs to be known at runtime, to execute shared/network code for example, that was built for a common target whose clock source is not know at compile time.

    I found this here
    ersmith: "So: I propose that we standardize for now on TAQOZ's use of $10 to $20 as _XIN, _CPUHZ, _CLKCFG, and _BAUD, with $0-$F reserved for a jump instruction and anything else the language runtime wants to use to initialize. _XIN is not likely to change at run time, so I'd be fine with moving that to the ROM area, but the other 3 values are pretty likely to be set by the runtime environment, so I think putting them in RAM makes sense."
    rogloh wrote: »
    Are there any cases where the original clock input frequency needs to be known at runtime, to execute shared/network code for example, that was built for a common target whose clock source is not know at compile time.
    Most microcontroller designs know SysCLK at compile time.
    However if P2 gets used for more microprocessor type tasks, and/or someone wants to actively scale SysCLK to preserve power, then a _CPUHZ is useful.
  • jmgjmg Posts: 14,027
    edited 2019-11-09 - 21:15:36
    Si5351A table example - placed at 0x8000 so can link or download separately as needed. Current default is 26.000MHz reference frequency to 20.000MHz CLK1 out.
    lcsc examples :

    Crystal, best ppm over wide temperature, in 2520 package :
    K2C260000910 KYX 26MHz ±10ppm SMD-2520 26MHz ±10ppm 9pF 40Ω ±10ppm -40~85℃ ±3ppm/yr 2996 In stock 500+ $0.0727

    Oscillator, best ppm specs VCTCXO
    VCTCXO 1XXA26000MAA KDS Daishinku 26MHz ±2ppm SMD-2520_4PAD 2.8V -30~85°C : ±0.5ppm, Vcc/Load :±0.1ppm, max Slope < 0.05ppm/°C -20~65°C VC ±9ppm ±1ppm/yr ±2.5ppm/5yr
    2524 In stock 500+ $0.2409

    ; ~~~~~~~~ Si5151A INIT ~~~~~~~~~~~~
    ; SI5351A Init Table, palced at 0x8000 for separate downloads via UB3 Boot loader
    ; For Non-std Xtals, Select Si5351C in clock builder, and choose CLKIN source, also Enable Xtal
    ; Then, remove Reg7 and Reg15 lines, and that changes to Si5351A and XTAL source. PLL settings do not change.
    ; See also AN619
            CSEG   AT 08000H   ;  Table offset UB3 
    
    Table_Is_26Mto20M   EQU 1
    Table_Is_XtalEnable EQU 0
    
    If Table_Is_26Mto20M       ; Confirms as 19.230773*26/25 = 20.00000392 Loads in 3.138ms
    Xtal_CLK1_Lines:
           DB       (Xtal_CLK1_Lines_End-($+1)) >> 1    ; Number of regAdr.RegDat pairs in table
    ; Overview
    ; ========
    ; Part:               Si5351C
    ; Project File:       Si5351A-B-26MCLKIN_20MCLK1.slabtimeproj
    ; Created By:         ClockBuilder Pro v2.38 [2019-10-31]
    ; Timestamp:          2019-11-07 16:54:41 GMT+13:00
    ; 
    ; Design
    ; ======
    ; Inputs:
    ;     IN0: 25 MHz
    ;     IN1: 26 MHz
    ; 
    ; Outputs:
    ;    OUT1: 20 MHz Enabled LVCMOS 8 mA  Offset 0.000 s 
    ; 
    ; Frequency Plan
    ; ==============
    ; PLL_A:
    ;    Enabled Features = None
    ;    Fvco             = 900 MHz
    ;    M                = 34.6153846153846153... [ 34 + 8/13 ]
    ;    Input0:
    ;       Source           = CLKIN
    ;       Source Frequency = 26 MHz
    ;       P                = 1  (2^0)
    ;       Fpfd             = 26 MHz
    ;    Output1:
    ;       Features       = None
    ;       Disabled State = StopLow
    ;       R              = 1  (2^0)
    ;       Fout           = 20 MHz
    ;       N              = 45
    ; 
            DB      0x0002,0x43
            DB      0x0003,0x00
    ;        DB     #0x0007,0x01  # remove this line, Si5351C tag
    ;        DB     #0x000F,0x04  # remove this to flip Si5351C.CLKIN to Si5351A.XTAL IN
            DB      0x0010,0x8C
            DB      0x0011,0x8C  ; << CLK1 Enable  Edited 0x0F  try cleaner init, so disable here, enable later... ?
            DB      0x0012,0x8C
            DB      0x0013,0x8C
            DB      0x0014,0x8C
            DB      0x0015,0x8C
            DB      0x0016,0x8C
            DB      0x0017,0x8C
            DB      0x001A,0x00
            DB      0x001B,0x0D
            DB      0x001C,0x00
            DB      0x001D,0x0F
            DB      0x001E,0x4E
            DB      0x001F,0x00
            DB      0x0020,0x00
            DB      0x0021,0x0A
            DB      0x0032,0x00
            DB      0x0033,0x01
            DB      0x0034,0x00
            DB      0x0035,0x14
            DB      0x0036,0x80
            DB      0x0037,0x00
            DB      0x0038,0x00
            DB      0x0039,0x00
            DB      0x005A,0x00
            DB      0x005B,0x00
            DB      0x0095,0x00
            DB      0x0096,0x00
            DB      0x0097,0x00
            DB      0x0098,0x00
            DB      0x0099,0x00
            DB      0x009A,0x00
            DB      0x009B,0x00
            DB      0x00A2,0x00
            DB      0x00A3,0x00
            DB      0x00A4,0x00
            DB      0x00B7,0x92  ;   0x92 => 25.00027MHz (8pF)  0xD2 =>  24.99977 (10pF) 0x12  => 25.00717  Ctr Test: 0x92  19.230770*26/25 = 20.0000008MHz from 26.000MHz
            DB      0x0011,0x0F  ; << added  CLK1  Enable delayed to last, to avoid errant bursts at power up.
            DB      0xFF,00  
    Xtal_CLK1_Lines_End:
            DB      0xFF,00  
    ENDIf ;  Table_Is_26Mto20M
    
    If Table_Is_XtalEnable
    Xtal_CLK1_Lines:
           DB       (Xtal_CLK1_Lines_End-($+1)) >> 1    ; Number of regAdr.RegDat pairs in table
    ; now the table - every line here sends  Start.Adr5351.RegAdr.RegVal.STOP
    ; This can be an include file, or it can be ABS located on a UB3 page to allow Boot-re-table.
    ;       DB       0x00FF,75    ; Trap unused Reg255, 15 is 400kHz i2c  Reg255 = 75 -> 99.579kHz i2c
    ;
           DB       0x0010,0x80  ; Disable CLK0 driver 0x8C CLK0_PDN MS0_INT MS0_SRC CLK0_INV CLK0_SRC[1:0] CLK0_IDRV[1:0]  Reset value = 0000 0000
           DB       0x0011,0x03  ; Edit to 0x03 for FORCE Xtal -> CLK1, 8mA 0x0F is PLL
           DB       0x0012,0x80  ; Disable CLK2 driver 
           DB       0x00B7,0x92  ; 7:6 XTAL_CL[1:0]    0x92 => 25.00027MHz (8p)  0xD2 =>  24.99977 (10p) 0x12  => 25.00717
           DB       0x00BB,0x40  ; << added, 187.6 XO_FANOUT_EN  IMPORTANT - From a clean reset, this line alone is enough to give Xtal on all CLK0,1,2
    Xtal_CLK1_Lines_End:
    ENDIf ;  Table_Is_XtalEnable
    
    
  • jmgjmg Posts: 14,027
    Startup operation, from PC-USB insert to Si5351 SCL and CLK1 out, & Si5351.SCL and P2.RESET pulse.
    P2 starts boot ~ 5.5ms after reset release
  • Cluso99Cluso99 Posts: 15,477
    edited 2019-11-09 - 21:41:28
    @jmg
    Curious that you chose an oscillator that has a recommended operating voltage of 2V8 and recommended limits of 2V66-2V94.

    And when did we change to using 26MHz as the new base frequency? I thought Peter was changing the oscillator back to 20MHz?

    So now we have P2D2 original at 12MHz, P2EVAL at 20MHz (both IIRC), and P2D2R2 at 20MHz or 26MHz, and you are recommending a 26MHz OSC ???
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • jmgjmg Posts: 14,027
    edited 2019-11-09 - 23:33:54
    Cluso99 wrote: »
    @jmg
    Curious that you chose an oscillator that has a recommended operating voltage of 2V8 and recommended limits of 2V66-2V94.

    Yes, the rating is 4.6V Abs MAX and they do a range of spec versions.
    From KDS website : https://www.kds.info/product/dsa221sdn-1/
    Supply Voltage Range +1.68~+3.5V
    Supply Voltage (VCC) +1.8V / +2.6V / +2.8V / +3.0V / +3.3V

    2v8 is a common default, but they can work fine on 3v3, with a minor ppm shift (smaller than the reflow ppm shift).

    Cluso99 wrote: »
    ... I thought Peter was changing the oscillator back to 20MHz?
    So now we have P2D2 original at 12MHz, P2EVAL at 20MHz (both IIRC), and P2D2R2 at 20MHz or 26MHz, and you are recommending a 26MHz OSC ???

    Yes to both questions :)
    If you join the dots above, you see the init code runs 26MHz into the Si5351A and 20.000MHz into the P2
  • jmg wrote: »
    Cluso99 wrote: »
    @jmg
    Curious that you chose an oscillator that has a recommended operating voltage of 2V8 and recommended limits of 2V66-2V94.

    Yes, the rating is 4.6V Abs MAX and they do a range of spec versions.
    From KDS website : https://www.kds.info/product/dsa221sdn-1/
    Supply Voltage Range +1.68~+3.5V
    Supply Voltage (VCC) +1.8V / +2.6V / +2.8V / +3.0V / +3.3V

    2v8 is a common default, but they can work fine on 3v3, with a minor ppm shift (smaller than the reflow ppm shift).
    Curious...
    I see no information as to what shift you get when operating at 3V3 rather than the specified 2V8 ???
    In fact, a quick look doesn't show the difference between DSA/DSB/DSB..SDNB except maybe the third has a standby function.

    You seem to be so concerned about using 1-2ppm but then operate outside the recommended supply voltage. Doesn't make sense to me???

    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • jmgjmg Posts: 14,027
    Cluso99 wrote: »
    Curious...
    I see no information as to what shift you get when operating at 3V3 rather than the specified 2V8 ???
    In fact, a quick look doesn't show the difference between DSA/DSB/DSB..SDNB except maybe the third has a standby function.

    You seem to be so concerned about using 1-2ppm but then operate outside the recommended supply voltage. Doesn't make sense to me???
    The primary number I target is the drift over temperature, as the reflow dominates initial ppm, and anyone can trim initial variances.

    You can easily get a ppm MAX indicator from the data, that specs 0.1ppm max per 140mV.
    That points to a 0.357ppm movement (max) due to Vcc, which as I mentioned, is well under the reflow variance. Does it now make sense ?

  • I'm working with 25MHz crystals at present and may change to 26MHz later once I evaluate them but intend to have the clock gen programmed to always output 20MHz for compatibility.

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