ON Semi figured out the VIO problem!!!!

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  • cgraceycgracey Posts: 11,641
    edited 2019-09-07 - 10:56:41
    The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?

    When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.
  • evanhevanh Posts: 7,648
    edited 2019-09-07 - 11:30:38
    I've bit the bullet and started testing the v1 chip in my Eval board ... Just done a slow rise (by hand with a bench top supply) in VIO voltage on V4855.

    With VDD = 1.8 Volts there is no current draw on V4855 all the way up to 5.0 volt. Didn't want to try higher.
    With VDD = 0.0 Volts, V4855 current rises linearly up to 1.8 mA at 5.0 volts. But also rises at a different linear grade of about 50% of this current on other attempts. I even accidentally reached 5.12 Volts at one point.

    No sign of any crowbarring happing so far.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs. By doing that, we can more accurately measure their mass, and determine whether scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    I've bit the bullet and started testing the v1 chip in my Eval board ... Just done a slow rise (by hand with a bench top supply) in VIO voltage on V4855.

    With VDD = 1.8 Volts there is no current draw on V4855 all the way up to 5.0 volt. Didn't want to try higher.
    With VDD = 0.0 Volts, V4855 current rises linearly up to 1.8 mA at 5.0 volts. But also rises at a different linear grade of about 50% of this current on other attempts. I even accidentally reached 5.12 Volts at one point.

    No sign of any crowbarring happing so far.

    I wonder how much warning you'll get before it latches up and fries.
  • All this drama is the cost of having custom I/O circuits.

    If we used ON's I/O circuits, there would be no surprises, but then we wouldn't have DAC, ADC, variable drive levels, comparators, etc.
  • I can mount some of the P2ES chips I have onto my P2D2 boards and test them with my DP832 digital PSU or even another P2D2 controlling the programmable switchers on the new P2D2 board. I hate to do it but I can treat these chips, or some of them anyway, as burners.

    Chip, is there anything I can do to help?

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  • cgraceycgracey Posts: 11,641
    edited 2019-09-07 - 11:54:25
    I can mount some of the P2ES chips I have onto my P2D2 boards and test them with my DP832 digital PSU or even another P2D2 controlling the programmable switchers on the new P2D2 board. I hate to do it but I can treat these chips, or some of them anyway, as burners.

    Chip, is there anything I can do to help?

    Peter, don't worry about doing any destructive testing. ON has that under control now. Just have fun.
  • cgracey wrote: »
    Peter, don't worry about doing any destructive testing. ON has that under control now. Just have fun.

    Awwhh, no smoke, no fun :(


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  • ErNaErNa Posts: 1,267
    edited 2019-09-07 - 11:58:42
    It is easy to spend money, if it's not your own. My advise is: if there is a known risk, try to remove it. So the money spent to improve the custom pins is well spent. It's just to build a wall to encapsule a problem, what is alway cheaper than to build a wall to protect from the follow ups of a known problem. On the other hand: why not make the I/O-pins an ON-standard pin? That could promote Parallax too.
    no reason to reason if you feel feelings: in love with the propeller
  • evanhevanh Posts: 7,648
    edited 2019-09-07 - 12:16:14
    cgracey wrote: »
    I wonder how much warning you'll get before it latches up and fries.
    I've got a 330 ohm wire wound series resistor on that supply in the hopes that any latch-up will not be enough to fry anything. As a detail, the VIO voltage measurement is made at the Eval board, so the bench top was actually set higher when there was current flowing.

    PS: I've just completed testing the digital I/O functions of that group of pins. All seems good.
    PPS: Another detail - The linear rise in current starts from VIO = 0.7 volts.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs. By doing that, we can more accurately measure their mass, and determine whether scientists have systematically been underestimating how much matter they contain."
  • cgraceycgracey Posts: 11,641
    edited 2019-09-07 - 12:17:10
    ErNa wrote: »
    It is easy to spend money, if it's not your own. My advise is: if there is a known risk, try to remove it. So the money spent to improve the custom pins is well spent. It's just to build a wall to encapsule a problem, what is alway cheaper than to build a wall to protect from the follow ups of a known problem. On the other hand: why not make the I/O-pins an ON-standard pin? That could promote Parallax too.

    I think that once we can pass all their tests, our quality would be considered as good as their own. I wonder if they'd be interested in some deal like that.

    When I designed the I/O pad, I put all the logic inside it, using 3.3V circuitry. If I knew I could have relied on faster-running core-logic synthesis, I would have done only the bare minimum in 3.3V logic. That would have enabled the pin to clock faster.
  • evanh wrote: »
    cgracey wrote: »
    I wonder how much warning you'll get before it latches up and fries.
    I've got a 330 ohm wire wound series resistor on that supply in the hopes that any latch-up will not be enough to fry anything. As a detail, the VIO voltage measurement is made at the Eval board, so the bench top was actually set higher when there was current flowing.

    PS: I've just completed testing the digital I/O functions of that group of pins. All seems good.
    PPS: Another detail - The linear rise in current starts from VIO = 0.7 volts.

    I'm glad nothing got broken.
  • Whoa! The amount of current can be way higher! I just got 5 mA at only 2.5 Volts ...

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs. By doing that, we can more accurately measure their mass, and determine whether scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    Whoa! The amount of current can be way higher! I just got 5 mA at only 2.5 Volts ...

    So, maybe you developed a resistive path to GND?
  • cgracey wrote: »
    The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?

    When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.

    If you were to add the extra guard-rings, would they have any downside to IO performance in any mode?

    Are all parties certain of the fix (that it will work first time without any side effects) ? - ie. 50K would be the last payment for perfection, and not a peek into another box of Pandora ?

    Is this "simply" a specification issue... ie. if the P2 IOs were specified at typical 3.3V, maximum 4V, then latch-ups would not be an issue with that being below the 35%, 4.4V threshold.

    For customers requiring tougher IOs, I think adding external protection is typical, and probably likely anyway for industrial applications.

    Is there a specific reason that aiming for a higher maximum IO voltage would benefit sales of this version of P2 ?



    I think the trade-off concern would be a crucial deciding point for me...

    ie. would having the IOs made tougher lower the performance of certain SmartPin features?

    In that case, and with what information I have, I'd look toward keeping the current chip and releasing it with the relevant maximum voltage specification, and perhaps some example circuits of external protection for different purposes (ADC, simple IO, etc..)


    In the future, perhaps after a year of sales and market feedback, you might consider a sibling, perhaps P2C4 (4 core version), and that could have the extra guard-rings added if appropriate for tougher environments.

  • Adding guard rings has no ill performance consequence. They don"t even get expressed in the source schematic. It's just a note to the layout guy.
  • evanhevanh Posts: 7,648
    edited 2019-09-07 - 12:30:24
    cgracey wrote: »
    evanh wrote: »
    Whoa! The amount of current can be way higher! I just got 5 mA at only 2.5 Volts ...
    So, maybe you developed a resistive path to GND?
    Nope, now it's only 0.49 mA at 5.0 Volts. Each time I reset to 0.0 Volts I get a different slope above 0.7 Volts.

    PS: These VIO currents only occur when VDD = 0.0 Volts.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs. By doing that, we can more accurately measure their mass, and determine whether scientists have systematically been underestimating how much matter they contain."
  • VonSzarvas wrote: »
    cgracey wrote: »
    The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?

    When we call it "final', we must pay them $95k to transition the design to manufacturing mode. Meanwhile, another respin involving just the pad frame will cost $50k..$60k.

    If you were to add the extra guard-rings, would they have any downside to IO performance in any mode?

    Are all parties certain of the fix (that it will work first time without any side effects) ? - ie. 50K would be the last payment for perfection, and not a peek into another box of Pandora ?

    Is this "simply" a specification issue... ie. if the P2 IOs were specified at typical 3.3V, maximum 4V, then latch-ups would not be an issue with that being below the 35%, 4.4V threshold.

    For customers requiring tougher IOs, I think adding external protection is typical, and probably likely anyway for industrial applications.

    Is there a specific reason that aiming for a higher maximum IO voltage would benefit sales of this version of P2 ?



    I think the trade-off concern would be a crucial deciding point for me...

    ie. would having the IOs made tougher lower the performance of certain SmartPin features?

    In that case, and with what information I have, I'd look toward keeping the current chip and releasing it with the relevant maximum voltage specification, and perhaps some example circuits of external protection for different purposes (ADC, simple IO, etc..)


    In the future, perhaps after a year of sales and market feedback, you might consider a sibling, perhaps P2C4 (4 core version), and that could have the extra guard-rings added if appropriate for tougher environments.

    Good questions.

    While 4.62V seems extreme, spikes can happen incidentally in a design. ON seems to think it's a healthy margin to accommodate.
  • cgracey wrote: »
    Adding guard rings has no ill performance consequence. They don"t even get expressed in the source schematic. It's just a note to the layout guy.

    OK, that makes the choice tougher then!

    I still don't understand the need to specify the IOs beyond 4V, and thus test them beyond 4.4V, which is already significantly above the normal maximum operating voltage. I suppose if there's a good reason for that, and if the update is certain, then maybe you do need to think about finishing this off right. However painful.

    Shame this test wasn't included on the first spin, as you would have spotted this and rectified it. Maybe ON would be willing to accept some goodwill as your talking with them, and help you get this done right and into production.
  • Will OnSemi guarantee it will pass the 40% test if they add the guard rings? Somehow, I doubt it...
    You could add the rings and still be in the same position as now...
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  • Rayman wrote: »
    Will OnSemi guarantee it will pass the 40% test if they add the guard rings? Somehow, I doubt it...
    You could add the rings and still be in the same position as now...

    Exactly my concern too. Something to liaise with engineering for clarity.
  • RaymanRayman Posts: 9,647
    edited 2019-09-07 - 12:50:31
    I just looked up one of OnSemi's microcontrollers... It is rated for VDD from 2.7 to 3.6 V with an absolute max. of 4.6 V.
    So, seems they do spec there own chips to well above the specified voltage.

    But, I don't think I've heard of a problem with P1 failing in regular use... Most issues I've seen are when somebody puts 5 V where the 3.3 V goes... (or, trying to drive a motor directly and not accounting for inductive spikes)
    It's a tough call... I don't think P1 would survive 4.6 V in quantity. The PLLs tend to fail...

    There's "bird in hand being worth 2 in bush" and also "if it ain't broke, don't fix it"...
    But, on other hand, sounds like the guard rings are an obvious improvement with relatively low risk or effort to implement...
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  • evanhevanh Posts: 7,648
    edited 2019-09-07 - 13:32:28
    It looks like the slower the rise across 0.7 Volts, the steeper the slope becomes. A quick power up produces a current of less than 1.0 uA at 5.0 Volts.

    EDIT: Reaches 1.0 uA at 5.27 Volts, and 2.0 uA at 5.63 Volts, and 3.0 uA at 5.80 Volts. EDIT2: 4.0 uA at 5.91 Volts, and 5.0 uA at 6.00 Volts, and 6.0 uA at 6.06 Volts, and 7.0 uA at 6.13 Volts, and 8.0 uA at 6.18 Volts. EDIT3: 10.0 uA at 6.26 Volts, and 20.0 uA at 6.53 Volts, and 30.0 uA at 6.69 Volts, and 40.0 uA at 6.80 Volts.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs. By doing that, we can more accurately measure their mass, and determine whether scientists have systematically been underestimating how much matter they contain."
  • I wonder if you can do a deal with ON such that they can use your ADC/DAC circuits ???

    These circuits have certainly cost many arms and legs along the way :(
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  • Cluso99 wrote: »
    I wonder if you can do a deal with ON such that they can use your ADC/DAC circuits ???

    These circuits have certainly cost many arms and legs along the way :(
    Yes, that's what I want to say:

    On the other hand: why not make the I/O-pins an ON-standard pin? That could promote Parallax too.
    But the aussies are the better dealmakers, seems. Maybe someone sponsers the tariffs of a flight for you to negociate a best deal ever with ON? Meeting in lucky Dothan? I would love to contribute!
    no reason to reason if you feel feelings: in love with the propeller
  • David BetzDavid Betz Posts: 13,468
    edited 2019-09-07 - 14:22:01
    ErNa wrote: »
    On the other hand: why not make the I/O-pins an ON-standard pin?
    Because Propeller users are obsessed with video and we need the DACs to do that! :smile:

  • jmgjmg Posts: 13,838
    edited 2019-09-07 - 15:44:02
    cgracey wrote: »
    The ON boss said that he could get some kind of waiver on this test, in order to facilitate production. That would mean that this would be our final silicon. My gut is uneasy about that. What do you guys think?

    He makes a valid point.
    Personally, I would measure the latch up injection currents before making the call.
    A static ABS MAX of +30% is tolerable, if the latch up current is tolerable.
    Ie 200mA+ is ok.
  • David Betz wrote: »
    ErNa wrote: »
    On the other hand: why not make the I/O-pins an ON-standard pin?
    Because Propeller users are obsessed with video and we need the DACs to do that! :smile:

    I translate: Parallax should offer ON to use the I/O structure of the propeller ][ with all the features like DAC-ADC-quadrature-++++ as a general purpose building block to use in their other products. These features will always be linked back to Parallax and hopefully others will find their way to the propeller. Why do we fear to make Rocklin great with great ideas?
    no reason to reason if you feel feelings: in love with the propeller
  • evanh wrote: »
    It looks like the slower the rise across 0.7 Volts, the steeper the slope becomes. A quick power up produces a current of less than 1.0 uA at 5.0 Volts.

    EDIT: Reaches 1.0 uA at 5.27 Volts, and 2.0 uA at 5.63 Volts, and 3.0 uA at 5.80 Volts. EDIT2: 4.0 uA at 5.91 Volts, and 5.0 uA at 6.00 Volts, and 6.0 uA at 6.06 Volts, and 7.0 uA at 6.13 Volts, and 8.0 uA at 6.18 Volts. EDIT3: 10.0 uA at 6.26 Volts, and 20.0 uA at 6.53 Volts, and 30.0 uA at 6.69 Volts, and 40.0 uA at 6.80 Volts.

    Are you not seeing any functional problems after 6.80V exposure? By the time you got that high, I imagine something had blown out along the way.
  • ErNa wrote: »
    David Betz wrote: »
    ErNa wrote: »
    On the other hand: why not make the I/O-pins an ON-standard pin?
    Because Propeller users are obsessed with video and we need the DACs to do that! :smile:

    I translate: Parallax should offer ON to use the I/O structure of the propeller ][ with all the features like DAC-ADC-quadrature-++++ as a general purpose building block to use in their other products. These features will always be linked back to Parallax and hopefully others will find their way to the propeller. Why do we fear to make Rocklin great with great ideas?

    With royalties back to Parallax, of course...
  • ErNa wrote: »
    David Betz wrote: »
    ErNa wrote: »
    On the other hand: why not make the I/O-pins an ON-standard pin?
    Because Propeller users are obsessed with video and we need the DACs to do that! :smile:

    I translate: Parallax should offer ON to use the I/O structure of the propeller ][ with all the features like DAC-ADC-quadrature-++++ as a general purpose building block to use in their other products. These features will always be linked back to Parallax and hopefully others will find their way to the propeller. Why do we fear to make Rocklin great with great ideas?

    ON's pins have a certain height and form factor, which has got to be different than ours.

    I think the nearest they could do is adapt our schematic into their form factor, which would need lots of re-laying out, and wouldn't work for our chip, anyway.
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