ON Semi figured out the VIO problem!!!!

I got a call today from the engineering boss at On Semi and he said they now realize what's triggering the latch-up destruction on VIO pins.

Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.

This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.

I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.

So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.

I'm really glad that we know what the problem is now.
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Comments

  • Fantastic news, Chip. Achieving certainty/explanation has seemed so elusive with this
  • cgracey wrote: »
    I got a call today from the engineering boss at On Semi and he said they now realize what's triggering the latch-up destruction on VIO pins.

    Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.

    This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.

    I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.

    So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.

    I'm really glad that we know what the problem is now.
    When you spin the chip to fix this problem will you re-synthesize or just use the current digital stuff as-is? I guess I'm wondering if there are likely to be instruction changes with this re-spin?
  • Great news Chip! The wait to get the guards is a bummer, but the ability to produce a couple dozen Eval boards is great news.
  • David Betz wrote: »
    When you spin the chip to fix this problem will you re-synthesize or just use the current digital stuff as-is? I guess I'm wondering if there are likely to be instruction changes with this re-spin?

    No need to resynthesize. The core is fine.

    This turn will just be some GDS changes to the custom pad frame elements.

    So, no tool impact.
  • cgraceycgracey Posts: 11,747
    edited 2019-09-06 - 21:38:08
    Tubular wrote: »
    Fantastic news, Chip. Achieving certainty/explanation has seemed so elusive with this

    Yeah, it was impossible without the information that the V-stress test was in use. We had asked in so many ways, in excruciating detail, to discover this, but the test technician wasn't aware of it, himself, so we couldn't get any affirmation that anything unexpected was going on.
  • If I had just gone out there a few weeks ago, I would have seen VIO driven to 4.62V, right away. I should have gone.
  • Glad to hear we have a definitive cause.

    C.W.

  • The ON engineering boss said that they are going to do a regular latch-up test on the new chip to see if it reveals any other latent problems. This may result in some layout changes, as well.
  • RaymanRayman Posts: 9,792
    edited 2019-09-06 - 22:18:06
    Great! I had a feeling it was the tester that was the problem...
    I didn't believe that substrate resistance stuff...
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  • P1 doesn't do so good either when you hit with 5 VDC...
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  • cgracey wrote: »
    David Betz wrote: »
    When you spin the chip to fix this problem will you re-synthesize or just use the current digital stuff as-is? I guess I'm wondering if there are likely to be instruction changes with this re-spin?

    No need to resynthesize. The core is fine.

    This turn will just be some GDS changes to the custom pad frame elements.

    So, no tool impact.
    That's good to hear. Do you know how much you're going to sell the new eval boards for? I can't recall what the last batch cost.

  • David Betz wrote: »
    cgracey wrote: »
    David Betz wrote: »
    When you spin the chip to fix this problem will you re-synthesize or just use the current digital stuff as-is? I guess I'm wondering if there are likely to be instruction changes with this re-spin?

    No need to resynthesize. The core is fine.

    This turn will just be some GDS changes to the custom pad frame elements.

    So, no tool impact.
    That's good to hear. Do you know how much you're going to sell the new eval boards for? I can't recall what the last batch cost.

    The old ones where $150.
    https://www.parallax.com/product/64000-es
  • Does the redesign mean the chip might survive if VIO is taken to 5 VDC?
    I suppose that would be nice...
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  • Rayman wrote: »
    Does the redesign mean the chip might survive if VIO is taken to 5 VDC?
    I suppose that would be nice...

    Well, it will be production tested to 4.62V. A design improvement might make it much better than that, but it will only be tested at ON Semi to 4.62V. Once we get new silicon, I will do some destructive checks to see where the limit is.
  • David Betz wrote: »
    cgracey wrote: »
    David Betz wrote: »
    When you spin the chip to fix this problem will you re-synthesize or just use the current digital stuff as-is? I guess I'm wondering if there are likely to be instruction changes with this re-spin?

    No need to resynthesize. The core is fine.

    This turn will just be some GDS changes to the custom pad frame elements.

    So, no tool impact.
    That's good to hear. Do you know how much you're going to sell the new eval boards for? I can't recall what the last batch cost.

    I think we will sell the new ones for $150, again.
  • Great new Chip. I bet Ken is dancing a jig... LOL

    Bean
  • Great to have a better understanding on this issue now Chip. Things had gone quiet here after a flurry of excitement when the P2 rev B came out and initially all looked good.

    I wonder how much delay to full production this change will introduce?

    Do you need to wait to get the remaining working P2's from this latest run packaged and sent out and tested by others to find any other remaining unknown issues before you commit to the next respin, or does it all go in parallel?
  • Great news, Chip. Now, that ON Semi has found the fault, and knowing that the fault is fixable, we can expect Chipmas. That was a major breakthrough.

    Kind regards, Samuel Lourenço
  • Rayman,
    It is still the substrate problem, that's why the guard rings are needed. Chip is just pointing that there was a undocumented testing change that started highlighting, in a severe way, the real problem.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • So glad to hear this is figured out now, and seems like it will not be hard or take long to fix.
    I assume the re-spin with this fix will still be a few months time before we have "new new" chips...
  • So now we see that the reason their tester was failing when all the previous chips seemed OK was a new test that increase VIO 40% above 3.3 V.
    That seems like a pretty brutal test to me...
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  • All this was very exciting, like a roller coaster.
  • Rayman wrote: »
    That seems like a pretty brutal test to me...
    Not as brutal as the missing current limit.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • I am going to ask if they have any other tests they can apply, so we can be sure to cover everything.

    Meanwhile, I asked him about the ESD test, which the chip passed. He said it passed the 4kV human body model and 2kV machine model, which is good.
  • rogloh wrote: »
    Great to have a better understanding on this issue now Chip. Things had gone quiet here after a flurry of excitement when the P2 rev B came out and initially all looked good.

    I wonder how much delay to full production this change will introduce?

    Do you need to wait to get the remaining working P2's from this latest run packaged and sent out and tested by others to find any other remaining unknown issues before you commit to the next respin, or does it all go in parallel?

    All the new features seem to work. We are going to send you a new-silicon P2 Eval Rev B on Monday, actually. Ersmith, EvanH, Peter, and a few others will be getting one, too. Hopefully, if there are any logic errors, you guys will discover them pretty soon. I am working on the documentation, again, so things will be ready.
  • Thanks Chip. I'll get those freezer packs out again.
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • »Panta rhei« You can not step into the same river twice. We all sometimes suffer from "I have changed nothing" when a systems shows a problem after routine maintenance. Things are in a flow and change always, happily not to the bad, but to the good. This showes us again: we have to rely on our fellow men, which we are ourselves. Whenever we act we have to do this carefully, drive change but not be driven to change, and we have to know for sure: the current situation is the result of many many experiments and we should know: we are responsible whenever we change something we are just not aware of. And so we are, if we are aware and for sure, we are responsible, if we just use a sledge hammer to improve the world.
    The Propeller is the result of careful thinking both of an individual, of individuals and of the community. Thats great.
    no reason to reason if you feel feelings: in love with the propeller

    How-2-TACHYON
  • Oh, at last the problem has been found :smiley:
    It’s a bit embarrassing for ON. Hopefully they’ll push the fixes thru quickly.
    Meanwhile you can get some more chips/boards out into more hands.
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  • jmgjmg Posts: 14,015
    cgracey wrote: »
    If I had just gone out there a few weeks ago, I would have seen VIO driven to 4.62V, right away. I should have gone.
    Do they have this 4.62v test limit as some part of the FAB recipe ?
    Seems like they have set this limit, based on what designs usually can tolerate.
    cgracey wrote: »
    Well, it will be production tested to 4.62V. A design improvement might make it much better than that, but it will only be tested at ON Semi to 4.62V. Once we get new silicon, I will do some destructive checks to see where the limit is.
    It could be useful to know where the present limit is, to give rules around ES2 use, and to find what gains are actually made by the changes.
    cgracey wrote: »
    I am going to ask if they have any other tests they can apply, so we can be sure to cover everything.

    Meanwhile, I asked him about the ESD test, which the chip passed. He said it passed the 4kV human body model and 2kV machine model, which is good.
    The way Nuvoton and Atmel spec is to give ESD kV like that, and latch up MAX injection currents and some absolute max values for Vdd/VIO, which are not usually as high as +40% on nominal.
    Users would not expect VIO to suddenly change, but they can expect ESD events and if enough current is also injected, that can trigger Usually high VIO impulse is a secondary outcome of a ESD event, it is not ‘operational’ or static.

    I would be curious to nail down existing limit values before hitting a revise button.
    Ie the failure trigger is not what anyone would consider normal use ?

  • cgraceycgracey Posts: 11,747
    edited 2019-09-07 - 10:49:34
    jmg wrote: »
    cgracey wrote: »
    If I had just gone out there a few weeks ago, I would have seen VIO driven to 4.62V, right away. I should have gone.
    Do they have this 4.62v test limit as some part of the FAB recipe ?
    Seems like they have set this limit, based on what designs usually can tolerate.
    cgracey wrote: »
    Well, it will be production tested to 4.62V. A design improvement might make it much better than that, but it will only be tested at ON Semi to 4.62V. Once we get new silicon, I will do some destructive checks to see where the limit is.
    It could be useful to know where the present limit is, to give rules around ES2 use, and to find what gains are actually made by the changes.
    cgracey wrote: »
    I am going to ask if they have any other tests they can apply, so we can be sure to cover everything.

    Meanwhile, I asked him about the ESD test, which the chip passed. He said it passed the 4kV human body model and 2kV machine model, which is good.
    The way Nuvoton and Atmel spec is to give ESD kV like that, and latch up MAX injection currents and some absolute max values for Vdd/VIO, which are not usually as high as +40% on nominal.
    Users would not expect VIO to suddenly change, but they can expect ESD events and if enough current is also injected, that can trigger Usually high VIO impulse is a secondary outcome of a ESD event, it is not ‘operational’ or static.

    I would be curious to nail down existing limit values before hitting a revise button.
    Ie the failure trigger is not what anyone would consider normal use ?

    They just tested a bunch of Rev A chips they had on hand, gradually increasing the VDD and VIO voltages until they started seeing VIO failures at +35%. That is our current baseline.

    The absolute-maximum rating in the data sheet will be much lower than that, of course.

    My understanding is that this V-stress test is part of their standard testing.
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