I got a call today from the engineering boss at On Semi and he said they now realize what's triggering the latch-up destruction on VIO pins.
Their test technician, who Wendy and I have been working with, realized yesterday that in the test suite for the new silicon, an additional test had been added that wasn't (but should have been) in the test suite for the original silicon. It's a V-stress test which raises VDD and VIO voltages 40% above 1.8V and 3.3V. This is what's been blowing out the VIO pins!!! This indicates that there is some design weakness in the chip regarding latch-up immunity at higher voltages, which may incidentally occur in a customer application.
This is funny, because Wendy and I had asked in a dozen different ways if ANYTHING had changed in the test suite, aside from the updated digital test patterns, and the answer was always "no", to paraphrase. It just wasn't making sense, but the tester seemed to play a role. Anyway, the tester WAS blowing up the chips.
I'm relieved that we now know what the trouble is, but it's frustrating to have lost a month diagnosing this problem, and even more so that this V-stress test wasn't applied to the first-version silicon, as it would have resulted in awareness of a problem that would have been already fixed in this new silicon. The fix is just placing guard rings around several N-wells, which is no big deal. At this point, though, it means new masks and a wafer run.
So, they are going to be able to package us up a few hundred new chips in the Amkor package. It will take a few weeks, at least. We will be able to build new P2 Eval boards immediately. They had tested two wafers out of six, before stopping after both probe cards had sustained damage to VIO pins. Many of those dies are now toast. They will need to re-probe those wafers, checking for excessive VIO current, or just probe virgin wafers which haven't been exposed to the V-Stress test, in order to get dies to send to Amkor for packaging.
I'm really glad that we know what the problem is now.