Giant wafer

This discussion was created from comments split from: P2 Eval Board Owners, I need your help!.
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  • jmgjmg Posts: 14,316
    .. as a small diversion from this talk on P2 wafer yields, this is today's news...

    Imagine the wafer yields on this thing ?! - no mention of how they cool it, but there are what look like mounting holes in the die !

    https://www.edacafe.com/nbc/articles/1/1693023/Cerebras-Systems-Unveils-Industrys-First-Trillion-Transistor-Chip
    "Optimized for AI work, the Cerebras Wafer Scale Engine (WSE) is a single chip that contains more than 1.2 trillion transistors and is 46,225 square millimeters. The WSE is 56.7 times larger than the largest graphics processing unit which measures 815 square millimeters and 21.1 billion transistors1. The WSE also contains 3,000 times more high speed, on-chip memory, and has 10,000 times more memory bandwidth."

    That monster makes the 'large' P2 die, look tiny... :)
  • Good grief! It is huge!

    What wafer size? Seems to me that thing is a wafer, basically.

    Yields may be expressed in terms of functioning processing units.

    80 percent chips, 90, 95, 100.

  • jmg wrote: »
    .. as a small diversion from this talk on P2 wafer yields, this is today's news...

    Imagine the wafer yields on this thing ?! - no mention of how they cool it, but there are what look like mounting holes in the die !

    https://www.edacafe.com/nbc/articles/1/1693023/Cerebras-Systems-Unveils-Industrys-First-Trillion-Transistor-Chip
    "Optimized for AI work, the Cerebras Wafer Scale Engine (WSE) is a single chip that contains more than 1.2 trillion transistors and is 46,225 square millimeters. The WSE is 56.7 times larger than the largest graphics processing unit which measures 815 square millimeters and 21.1 billion transistors1. The WSE also contains 3,000 times more high speed, on-chip memory, and has 10,000 times more memory bandwidth."

    That monster makes the 'large' P2 die, look tiny... :)

    Can we get that in a 40 pin DIP?
  • Maybe that will put Moore's law back on track...
  • potatohead,
    215mm x 215mm = 46224 sq mm.
    So 21.5cm x 21.5cm or about 8.46in x 8.46in
  • Looks like they just squared up a 300 mm wafer.
  • But will it run Crysis?

    (Sorry, I had to)
  • Yeah Chip, Roy it does.

    One wafer, one processing unit. Run what works on it, and make a lot of them. Sheesh.


  • I don't know how much leeway there is on a 300 mm wafer but that makes 304 mm diagonal. The alternative is the square has its corners clipped.
  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 00:42:29
    A 300mm wafer is ~70,000mm2. I’m not sure how much wastage there is around the edge.

    So this is over half of the wafer!!!

    Maybe they should just make a round chip :smiley:

    And what about power? Need a KW power supply? And it’s own air conditioner?

    Wonder what the speed is? Maybe 4-5GHz?

    Will it run Arduino ;)
  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 00:49:22
    There is 400,000 cores and 18GB SRAM 1 clock access. That’s 36KB per core.

    Or with 18GB it will run 4 copies of Windoze 10 at once ;)
  • Cluso99 wrote: »
    A 300mm wafer is ~70,000mm2. I’m not sure how much wastage there is around the edge.

    So this is over half of the wafer!!!
    It'll be the whole wafer trimmed to a single square. Problem is, as a square, it doesn't fit within 300 mm diameter.

  • evanhevanh Posts: 9,417
    edited 2019-08-20 - 01:19:09
    Aside from defect re-routing, it'll be a hell of job to package it. I'm presuming it's not quite a square and has rounded corners as a result. That probably won't really matter given the custom nature.

    Begs the question of why not just make it a round package and and not trim the wafer at all. Then they could use the whole 70,000 mm2.

  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 01:26:40
    evanh wrote: »
    Aside from defect re-routing, it'll be a hell of job to package it. I'm presuming it's not quite a square and has rounded corners as a result. That probably won't really matter given the custom nature.

    Begs the question of why not just make it a round package and and not trim the wafer at all. Then they could use the whole 70,000 mm2.
    Yeah, that’s what i was thinking. Since there really isn’t any point in the remaining space, may as well fill it up with a few more cores.
    Probably get another 100,000-150,000 cores and 4-7GB

    Any free engineering samples???
  • evanhevanh Posts: 9,417
    edited 2019-08-20 - 01:33:41
    Cluso99 wrote: »
    Yeah, that’s what i was thinking.
    Oops, so you were. Didn't read that far.

    I'm guessing they decided to make it square, externally at least, for everyone's sanity.

  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 01:49:51
    evanh wrote: »
    Cluso99 wrote: »
    A 300mm wafer is ~70,000mm2. I’m not sure how much wastage there is around the edge.

    So this is over half of the wafer!!!
    It'll be the whole wafer trimmed to a single square. Problem is, as a square, it doesn't fit within 300 mm diameter.
    It’s 215x215mm which requires 304mm dia so maybe the corners are slightly trimmed or a 300mm wafer is actually slightly more.

    Those large holes you see on the wafer are the I/O - you just hand solder wires to them :wink:
  • Doh! I'd read the headline elsewhere but not seen a photo. I see it has got rounded corners. :)

  • Moderators - could you move this to a separate thread please?
  • Great news, Chip!

    On the giant wafer chip I suspect the reason they squared the wafer is that there is an X-Y addressing scheme for the cores which doesn't deal well with the missing corners if they were to try to make use of the chords they discarded.
  • Cluso99 wrote: »
    Moderators - could you move this to a separate thread please?

    Done!

  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 08:36:22
    Thanks von :)

    I often wondered what the maximum die size was. Now we know... the whole wafer which is currently 300mm dia AFAIK. Thats ~70,000mm2.

    So, using OnSemi 200mm wafers at 180nm, that’s ~31,000mm2. This gives ~47B transistors in ~142mm square, or ~70B transistors on the whole wafer.

    Or another way, the P2 is 8.5mm sq = ~72mm2, so on a whole wafer we could fit ~430 P2’s or 3,440 P2 cores with 215MB Hub Ram. Of course it doesn’t quite scale like this, but it puts it in some perspective.
  • If that HUGE chip fits 1T transistors into 70,000 mm2, then it fits 1T/70k = 14.3M transistors per mm2.

    The P2 fits 32M transistors in 72.3 mm2, for a density of 32M/72.3 = 443k transistors per mm2.

    The density difference is 14.3M/443k = 32.3x. The HUGE chip process size must be about 180nm/sqrt(32.3) = 31.6nm. It's probably a 28nm process, which TSMC offers.

  • Far cry from the IBM 1130 AND 360.
  • cgracey wrote: »
    It's probably a 28nm process, which TSMC offers.
    The WSE is manufactured by TSMC on its advanced 16nm process technology

    https://www.businesswire.com/news/home/20190819005148/en/


  • Oh, I thought it was 70k mm2, but it's 46k mm2. I'll redo the math...


    If that HUGE chip fits 1T transistors into 46,000 mm2, then it fits 1T/46k = 21.7M transistors per mm2.

    The P2 fits 32M transistors in 72.3 mm2, for a density of 32M/72.3 = 443k transistors per mm2.

    The density difference is 21.7M/443k = 49x. The HUGE chip process size must be about 180nm/sqrt(49) = 25.7nm.

    We know it's a 16nm process, though.
  • Cluso99Cluso99 Posts: 16,096
    edited 2019-08-20 - 15:42:47
    IIRC the 386 was the first chip to reach 1M transistors.

    I’m drooling to think we could have a P2 with say 256 cores, each with 64KB private cog/lut, and a giant central hub of banked 256 x 1MB. Even at 180nm and 350MHz it would be awesome 😎

    I’d even settle for a list of failed cores and hub ram blocks.

    What would i do with it ? Dunno 🤷‍♂️
  • Giant die would be a more accurate thread title.
  • Wow!! That's crazy stuff !
    I've been reading about a project that was wanting to do the very same thing (Wafer-scale) since 1999 as a Smalltalk processor.
    The project is called SiliconSqueak. Merik Voswinkel and Jecel Assumpcao Jr. are the guys behind it.

    A quick google search found a few documents including a PHD dissertation all by the same guys.
    The project might prove an interesting read :-)

    https://www.researchgate.net/project/Agora-Wafer-Scale-Integration
    Dec 30th 2016

    https://www.researchgate.net/publication/312029203_Plurion_an_Object_Oriented_Microprocessor
    Jan 2005

    http://www.merlintec.com/download/jecel_phd_deposited.pdf
    May 2015

    http://www.merlintec.com/
    The Brazilian research company working on SiliconSqueak.

    J

  • Chip,
    it's 1.2 Trillion... :) time to redo the math again.
  • MJBMJB Posts: 1,154
    edited 2019-08-20 - 17:08:34
    cgracey wrote: »
    If that HUGE chip fits 1T transistors into 70,000 mm2, then it fits 1T/70k = 14.3M transistors per mm2.

    The P2 fits 32M transistors in 72.3 mm2, for a density of 32M/72.3 = 443k transistors per mm2.

    The density difference is 14.3M/443k = 32.3x. The HUGE chip process size must be about 180nm/sqrt(32.3) = 31.6nm. It's probably a 28nm process, which TSMC offers.

    the article says
    The WSE is manufactured by TSMC on its advanced 16nm process technology.

    as they probably need a lot of space for connectivity as well ...
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