P2 Eval Board Owners, I need your help!

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  • A bit late to the party, I had to dismount my eval board from a machine.

    Using a APPA 95 multimeter WIth common connection ( black) on a Ground pin. My initial reading on each pin starts around .1 meg ohm and slowly climbs upward to out of range at 40M ohm. Reversing the leads, (red lead on ground) once a pin is "Charged" from checking it with the original (black on ground) the meter shows negative resistance that trends back down as the caps are drained.

    Any chance the on-board caps are holding a charge (accumulated from static or otherwise) with enough energy to cause damage as a built-up charge drains through the probes?
  • cgracey wrote: »
    It looks pretty certain that this VIO short to GND is only in the new silicon.

    It's not on every die, though. So, we should be able to screen away the bad ones with a resistance test on the wafer prober. Then, we can still get some initial chips packaged.

    There are many chips on a single die. Correct? You submitted the drawings for a single chip. Correct?

    If only some of the dies have a defect then it's a manufacturing error. Correct?
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  • jmgjmg Posts: 14,106
    If only some of the dies have a defect then it's a manufacturing error. Correct?
    Broadly, usually.
    'manufacturing error' can mean a submitted clearance was positive, but below their specs (but that should be caught by DRC), or a contaminated mask, which would usually give same-die-bad flags.
    Or it can be post-fab handling, like ESD, or the PADS/Probe combination may be such the probes damage something, or maybe even something as basic as metal shards on the manual package prep (but that would be packaged parts only)
    Of course, it can be more than one of the above too..

  • kbash wrote: »
    A bit late to the party, I had to dismount my eval board from a machine.

    Using a APPA 95 multimeter WIth common connection ( black) on a Ground pin. My initial reading on each pin starts around .1 meg ohm and slowly climbs upward to out of range at 40M ohm. Reversing the leads, (red lead on ground) once a pin is "Charged" from checking it with the original (black on ground) the meter shows negative resistance that trends back down as the caps are drained.

    Any chance the on-board caps are holding a charge (accumulated from static or otherwise) with enough energy to cause damage as a built-up charge drains through the probes?

    I don't think there's any potential for damage due to cap charge. If the voltage ever climbed high enough, the chip would conduct a little current due to leakage and stop the voltage rise.
  • cgracey wrote: »
    It looks pretty certain that this VIO short to GND is only in the new silicon.

    It's not on every die, though. So, we should be able to screen away the bad ones with a resistance test on the wafer prober. Then, we can still get some initial chips packaged.

    There are many chips on a single die. Correct? You submitted the drawings for a single chip. Correct?

    If only some of the dies have a defect then it's a manufacturing error. Correct?

    The "die" is the chip, before being packaged. It's the wafer that holds many dies/chips.
  • I'm very curious and hopeful this was some kind of manufacturing error...
    How could the first batch not have this and the second one have it when only the pll was changed?
    Doesn't seem to make any sense...

    Hopefully, the fail rate is low enough that Parallax can still sell individual chips...
    Too bad really, seemed like things were going perfectly with HDMI an low power at high freq., etc...

    But, what to do now? I'm hopeful that Wendy can figure out what happened...

    BTW: If I were Chip, I think I'd think of myself as something of a Peter Pan with Wendy helping me out... I think I'm coming up with a screenplay...
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  • RaymanRayman Posts: 9,916
    edited 2019-08-16 - 20:17:05
    We really should bring in Jon "don't call him Jonny" to talk about a P2 documentary movie...

    Just watched Apollo 11. Ok, not exactly the same scale, but more relevant to me...

    I really feel the need for a Parallax documentary movie... Can I do it? (no, I'm an engineer and incredibly boring...)
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  • cgraceycgracey Posts: 11,925
    edited 2019-08-16 - 20:22:48
    I heard back from a senior engineer at ON Semi yesterday who said they are looking into the problem. He suspects that the 3.3V supply is somehow shorting to the substrate, and it may or may not be a metal issue. I agree that this is the problem, as someone here posited, since we could see that a VIO pin completely blew out, while its complementary GIO pin was fine, indicating that the current flowed through the many VSS (substrate/GND) connections, instead.

    All VIO (3.3V) circuits sit in deep N-wells and those wells' taps are connected to VIO. The substrate, in which all wells sit, is connected to VSS (core GND).

    Here are the deep N-well connections from the RESn pad circuit:

    Deep_N_Well_connections.png

    Note that there are two uses of deep N-wells in the RESn pad. First use is the 3.3V-to-1.8V level translator which has its deep N-well connected to VDD (1.8V). The second use is the external pin interface circuit which has its deep N-well connected to VIO (3.3V).

    If those deep N-wells tied to VIO were to break down due to some over-voltage on VIO, perhaps, VIO could wind up shorted to VSS (substrate/GND). Or, if there was some manufacturing defect, they could start out shorted to VSS.

    So, we are waiting now for ON Semi to build themselves some open-cavity chips which they can power up and view through an infra-red microscope, in order to determine the locales of the hot-spots. That information should lead them to determine what the nature of the problem is. The engineer said it could be a manufacturing problem. I think either the tester got into a mode of killing chips, or there actually is a manufacturing problem.

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  • cgraceycgracey Posts: 11,925
    edited 2019-08-16 - 20:25:49
    The senior ON Semi engineer said that on Monday, they are going to have their test engineer sort a whole wafer from the original silicon run, to see if this problem was present, at all, in the original silicon. All indications, so far, have been that this is a NEW problem.

  • jmgjmg Posts: 14,106
    cgracey wrote: »
    So, we are waiting now for ON Semi to build themselves some open-cavity chips which they can power up and view through an infra-red microscope, in order to determine the locales of the hot-spots. That information should lead them to determine what the nature of the problem is. The engineer said it could be a manufacturing problem. I think either the tester got into a mode of killing chips, or there actually is a manufacturing problem.
    That sounds like a good idea, and if the tester is a suspect ( & I think it should be, as this stage), maybe some of those open-cavity parts can bypass any probe testing ?
    What yields have they been getting this far ?


  • jmgjmg Posts: 14,106
    cgracey wrote: »
    If those deep N-wells tied to VIO were to break down due to some over-voltage on VIO, perhaps, VIO could wind up shorted to VSS (substrate/GND).
    Most ESD testing focuses on io PAD ESD, because when mounted VIO pins are well decoupled. Did they ESD test any of the power pins ?
    You could take your sample with the single failed VIO, and try to damage other VIO, with ESD ?

  • So, the IR camera is an obvious first step... Never heard of this in microscope form, but makes sense... Wonder if the FLIR chips can zoom in....
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  • cgraceycgracey Posts: 11,925
    edited 2019-08-16 - 21:15:55
    Rayman wrote: »
    We really should bring in Jon "don't call him Jonny" to talk about a P2 documentary movie...

    Just watched Apollo 11. Ok, not exactly the same scale, but more relevant to me...

    I really feel the need for a Parallax documentary movie... Can I do it? (no, I'm an engineer and incredibly boring...)

    You can make the movie. You are sufficiently interesting.

    Maybe it's just interesting to us because we are so involved in it. I think it is absolutely interesting, but it would take some effort to present it in some way that outsiders would get the idea that it's interesting, too.

    I have a friend in Red Bluff who's an inventor and entrepreneur. He retrofits old moving trucks with huge diesel-powered vacuums that can suck lots of air through HVAC ducts, while he uses compressed air to loosen dust. He cleaned our system at home once and it was like living in a new house, with really fresh air. He mainly does commercial buildings. Anyway, he is always collecting junk, like hardened-steel bed frames and old municipal buses on his property. He has these ideas for water skis that are like bikes, which could seriously maim a person. He's always welding things together. His wife is very logical and keeps things going. He does her clothes shopping, since it's not interesting to her. He's almost 60 and does back flips on his trampoline. A few years ago, he broke both his ankles at once doing that. Around that time, some welding slag dropped into his ear and he poured some dirty water into it and got an infection which paralyzed half his face for a while. He's always involved in the young men's programs at church and comes up with ideas for elaborate Scouting trailers that can't really be fabricated, directly. One of the boys cited him as "The Most-Interested Man" (a variation on "The Most-Interesting Man").

    Albert Einstein said, “I am enough of the artist to draw freely upon my imagination. Imagination is more important than knowledge. Knowledge is limited. Imagination encircles the world.”
  • Rayman wrote: »
    So, the IR camera is an obvious first step... Never heard of this in microscope form, but makes sense... Wonder if the FLIR chips can zoom in....

    Yeah, I don't know that lenses can pass IR, but it has sufficient resolution to see things of interest.
  • jmg wrote: »
    cgracey wrote: »
    So, we are waiting now for ON Semi to build themselves some open-cavity chips which they can power up and view through an infra-red microscope, in order to determine the locales of the hot-spots. That information should lead them to determine what the nature of the problem is. The engineer said it could be a manufacturing problem. I think either the tester got into a mode of killing chips, or there actually is a manufacturing problem.
    That sounds like a good idea, and if the tester is a suspect ( & I think it should be, as this stage), maybe some of those open-cavity parts can bypass any probe testing ?
    What yields have they been getting this far ?


    Their yield is secret. I asked recently and was only told that yield information is not shared with customers.
  • My guess is they have lots of interesting test gear. But the best gear might be what they have for 7-8nm ;)
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  • jmg wrote: »
    cgracey wrote: »
    If those deep N-wells tied to VIO were to break down due to some over-voltage on VIO, perhaps, VIO could wind up shorted to VSS (substrate/GND).
    Most ESD testing focuses on io PAD ESD, because when mounted VIO pins are well decoupled. Did they ESD test any of the power pins ?
    You could take your sample with the single failed VIO, and try to damage other VIO, with ESD ?

    Yes, they have 30 of the original chips which have passed all tests. They are going to zap them and then retest them. Haven't heard anything about this for a while. I will ask.
  • Cluso99 wrote: »
    My guess is they have lots of interesting test gear. But the best gear might be what they have for 7-8nm ;)

    I think their smallest process is 110nm.
  • Cluso99Cluso99 Posts: 15,536
    edited 2019-08-16 - 22:13:48
    cgracey wrote: »
    Cluso99 wrote: »
    My guess is they have lots of interesting test gear. But the best gear might be what they have for 7-8nm ;)

    I think their smallest process is 110nm.

    Yes, my comment wasn’t expressed well as I was meaning equipment used by TSMC etc that have really fine geometry. But I expect OnSemi have some nice stuff for their finer lines.

    BTW I had thought OnSemi now had 90 nm... Off to check google ;)

    Just checked and the finest I could see on OnSemi s website is various 180nm. But I also found 600nm and 700nm listed. Presume that theses would be for power fets etc.

    Posted it
    Yes, OnSemi,s finest plant is 110nm but they are purchasing Fab10 45nm from Global Foundaries and have an arrangement for GF to produce 45nm for OnSemi in the transition period 2019-2022.
    P3 here we come... ;)
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  • jmgjmg Posts: 14,106
    cgracey wrote: »
    Their yield is secret. I asked recently and was only told that yield information is not shared with customers.

    Well, yes, but I was meaning the yield on this shorted-IO issue, which is not really any manufacturing secret.... but may help to indicate more about the problem.

    I'm a little surprised they simply bus up all the IO and seem to go straight to scan testing, but I guess such shorted IO is so rare these days, they never thought of a check-each-pin-at-low current softer test sequence start...


  • jmgjmg Posts: 14,106
    cgracey wrote: »
    Yes, they have 30 of the original chips which have passed all tests. They are going to zap them and then retest them. Haven't heard anything about this for a while. I will ask.
    As well as checking the ESD if VIO pins, you could also check how they do fail, when they finally do ?
    FWIR, just an increase in leakage above some data-limit is enough to be considered a fail.
  • localrogerlocalroger Posts: 3,290
    edited 2019-08-16 - 23:04:18
    I didn't know that onSemi wouldn't tell their own customers about yield.

    I had an application a few years ago that required using resistors to do current limiting between a 5V CPU bus and the Prop pins. There were a couple of high speed signals that simply wouldn't work unless I used a smaller than recommended resistor (1K instead of 3k3). In most cases it was fine but I found that about 1 in 20 prop chips blew the pin. But if I burned a chip in for an hour or two it would work forever. I strongly suspected this might have something to do with the die's original position on the wafer when it was manufactured. So much for proving that...

    Anyway I created a burn-in procedure to weed out the weak chips and this was much cheaper than switching to a "real" 3v3 converter. Never had a single burnin survivor fail in the field, even after years of continuous use.
  • localroger wrote: »
    I didn't know that onSemi wouldn't tell their own customers about yield.

    I had an application a few years ago that required using resistors to do current limiting between a 5V CPU bus and the Prop pins. There were a couple of high speed signals that simply wouldn't work unless I used a smaller than recommended resistor (1K instead of 3k3). In most cases it was fine but I found that about 1 in 20 prop chips blew the pin. But if I burned a chip in for an hour or two it would work forever. I strongly suspected this might have something to do with the die's original position on the wafer when it was manufactured. So much for proving that...

    Anyway I created a burn-in procedure to weed out the weak chips and this was much cheaper than switching to a "real" 3v3 converter. Never had a single burnin survivor fail in the field, even after years of continuous use.

    I wonder if we could detect future failures by any metrics.

    How many chips failed out of how many teated?
  • ON Semi confirmed that they went through the GDS data used to make the reticles and there were no problems. So, seems like a manufacturing problem.

    Their test engineer got through the first of six wafers without incident. It was on the second wafer that probe pins got fried. Maybe just that one wafer is bad.

    If they implemented some resistance checks before applying power, then used ~200mA-limited supplies for VDD and VIO, they could screen all six wafers safely and get us some parts soon.
  • cgracey wrote: »
    ON Semi confirmed that they went through the GDS data used to make the reticles and there were no problems. So, seems like a manufacturing problem.

    Their test engineer got through the first of six wafers without incident. It was on the second wafer that probe pins got fried. Maybe just that one wafer is bad.

    If they implemented some resistance checks before applying power, then used ~200mA-limited supplies for VDD and VIO, they could screen all six wafers safely and get us some parts soon.
    That's encouraging. If they just have one bad wafer then we should be able to get some good chips from the others. Will they refund the thousands of dollars that they charged you for melted probe pins if it ends up being a manufacturing problem?
  • jmgjmg Posts: 14,106
    cgracey wrote: »
    ON Semi confirmed that they went through the GDS data used to make the reticles and there were no problems. So, seems like a manufacturing problem.

    Their test engineer got through the first of six wafers without incident. It was on the second wafer that probe pins got fried. Maybe just that one wafer is bad.

    If they implemented some resistance checks before applying power, then used ~200mA-limited supplies for VDD and VIO, they could screen all six wafers safely and get us some parts soon.

    Does 'got through the first of six wafers without incident' mean a 100% pass rate ? If yes, that helps exclude a FAB hard issue of damage photo images.]

    I'd also ask them how difficult it is to separate out the VIO pins, from the present all-bus-up they have ?
  • These are indeed some good news, after so much time of stress and concerns.
    cgracey wrote: »
    I wonder if we could detect future failures by any metrics.

    How many chips failed out of how many tested?

    As for the possibility of detecting future failures by any metrics, all the information I was able to gather on that subject by the last 24 hours, does indicates that you need to know the position of each and every defective die at the finished wafer.

    With the above information in hands and also knowing the causes of any failure at each individual die, the defective ones could be sorted, and the maps for each individual wafer can be completed.

    By analizing defect distribution, the cause(s) for each kind of defect become immediately evident.

    But, since OnSemi internal politics blocks forwarding such kind of information to its customers, they are the only ones able to know, how many units from each production lot had failed, and why.

    Despite I don't like such kind of objection to information sharing, I kind of understand why they do it that way.

    In big volume markets like semiconductor industry, where billions are constantly moving like sand blown by the wind, advertising any process yelds could be a sure path for being killed, or swalled by the competition.

  • Bad wafer is a totally believable failure mode. Although I suspect there will be some frantic staff meetings at onSemi trying to figure out how the eff-up happened.
  • cgracey wrote: »
    If they implemented some resistance checks before applying power, then used ~200mA-limited supplies for VDD and VIO, they could screen all six wafers safely and get us some parts soon.

    You mean the don't limit current during the test!? Who here would do that given the cost of the test fixture?
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  • I think they said the current limit was *cough* two amperes *cough*. Into a pin of a 180nm process chip, yeah, I think there's gonna be a really kickass ISO meeting at the fab soon.
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