New P2 Silicon

191012141517

Comments

  • localroger wrote: »
    I second going there physically and putting eyes on, Chip. In thirty-five years of troubleshooting stuff I've never learned to see through a telephone, and many times I've resolved an issue in five minutes once I could see the layout with my own eyes.

    I once drove 26 hours round trip to put eyes on a problem, only to solve it in 20 minutes once there. Sometimes, there is no way around it.
  • TubularTubular Posts: 3,685
    edited 2019-08-14 - 03:39:30
    I wonder whether the smartpin is somehow achieving an invalid state due to (minute) charge on the probes, as they are applied. Perhaps the application order really matters. I'm not sure why that would be

    Does there seem to be any quantization of the base current values? eg you mentioned 125 and 500mA - does that correspond to 1 and 4 jammed up pins?
  • JimFouch2 wrote: »
    localroger wrote: »
    I second going there physically and putting eyes on, Chip. In thirty-five years of troubleshooting stuff I've never learned to see through a telephone, and many times I've resolved an issue in five minutes once I could see the layout with my own eyes.

    I once drove 26 hours round trip to put eyes on a problem, only to solve it in 20 minutes once there. Sometimes, there is no way around it.

    That's about what kind of time I'm looking at, if I drove. I don't know if I trust my '97 Altima to make that trip, though.

    We are going to run some really simple tests tomorrow morning to see if we can ramp VIO up slowly with RESn, TESn, and VDD at GND. If that works, we'll add VDD. We've got to figure out how to cut the pie in half. It would be great if I didn't have to go out there. As it is, they don't want me there before Monday.
  • cgraceycgracey Posts: 11,711
    edited 2019-08-14 - 03:43:46
    Tubular wrote: »
    I wonder whether the smartpin is somehow achieving an invalid state due to (minute) charge on the probes, as they are applied. Perhaps the application order really matters. I'm not sure why that would be

    Does there seem to be any quantization of the base current values? eg you mentioned 125 and 500mA - does that correspond to 1 and 4 jammed up pins?

    Just plugging and unplugging the test head causes the current to change to a steady new value. There doesn't seem to be any granularity to the current values.
  • jmgjmg Posts: 13,920
    cgracey wrote: »
    We are going to run some really simple tests tomorrow morning to see if we can ramp VIO up slowly with RESn, TESn, and VDD at GND. If that works, we'll add VDD. ...

    A triangle wave applied to each VIO sequentially, then to all of them, could give a useful current drain scope capture.

    Does RESn need a SysCLK, and is it edge actioned anywhere ?

  • jmg wrote: »
    cgracey wrote: »
    We are going to run some really simple tests tomorrow morning to see if we can ramp VIO up slowly with RESn, TESn, and VDD at GND. If that works, we'll add VDD. ...

    A triangle wave applied to each VIO sequentially, then to all of them, could give a useful current drain scope capture.

    Does RESn need a SysCLK, and is it edge actioned anywhere ?

    The floating-state quiescent pin-circuit current peaks when the pin is at ~VIO/2.

    RESn is asynchronous.
  • jmgjmg Posts: 13,920
    cgracey wrote: »
    The floating-state quiescent pin-circuit current peaks when the pin is at ~VIO/2.

    Yes, that transition current should be << 1mA, per pin, right ?
    I was meaning the 3v3 supplies to ramp up/down.


  • jmg wrote: »
    cgracey wrote: »
    The floating-state quiescent pin-circuit current peaks when the pin is at ~VIO/2.

    Yes, that transition current should be << 1mA, per pin, right ?
    I was meaning the 3v3 supplies to ramp up/down.


    It's 50uA peak, per pin. That would total to about 3.2mA if they were each at the transition point.
  • So much current flows sometimes, that the VIO probe tip melts. The tester probably supplied its maximum current of 2A. A VIO pin can, at most, normally pass 200mA, in the case of its four I/O pins outputting highs while shorted to GND. It probably took several times that much current to melt that probe tip.
  • cgracey wrote: »
    All 16 VSS pads are tied together on the die and go to GND.

    Each of the 16 VIO pads are unique and go to a pin.

    Each of the 16 GIO pads are unique and go to GND.
    And VDD?

    It would be interesting to know if the VIO current returns by GIO or VSS. Seems like it's not the pin's own GIO because the GIO probes aren't melting.
    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • cgraceycgracey Posts: 11,711
    edited 2019-08-14 - 05:55:30
    All 16 VDD pads are tied together on the die.

    EDIT: "VDD" here was orginally VSS, which was wrong.
  • cgraceycgracey Posts: 11,711
    edited 2019-08-14 - 04:21:30
    cgracey wrote: »
    All 16 VSS pads are tied together on the die and go to GND.

    Each of the 16 VIO pads are unique and go to a pin.

    Each of the 16 GIO pads are unique and go to GND.
    And VDD?

    It would be interesting to know if the VIO current returns by GIO or VSS. Seems like it's not the pin's own GIO because the GIO probes aren't melting.

    Good question. Seems like it might have been shared by all the VSS pins, doesn't it?
  • SaucySolitonSaucySoliton Posts: 247
    edited 2019-08-14 - 05:24:34
    cgracey wrote: »
    Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.


    A certain amount of over-travel is required after the first probe makes contact with the wafer, for two reasons:

    to guarantee that all probes have made contact (to account for non-planarity of the wafer)
    to break through the thin oxidized layer (if the metal pad is Aluminum) on the pad
    https://en.wikipedia.org/wiki/Non-contact_wafer_testing

    What if the VIO is shorted to VSS? Then some of the resistance would be from the oxide layer, which could vary. The rest would be from the probe, which I'd expect to be significant at 100s of mA.

    Would it be possible to test resistance of the VIO to GIO before applying power? Is a shorted VIO a probable defect?

    James https://github.com/SaucySoliton/

    Invention is the Science of Laziness
  • jmgjmg Posts: 13,920
    edited 2019-08-14 - 05:41:34
    cgracey wrote: »
    So much current flows sometimes, that the VIO probe tip melts. The tester probably supplied its maximum current of 2A. A VIO pin can, at most, normally pass 200mA, in the case of its four I/O pins outputting highs while shorted to GND. It probably took several times that much current to melt that probe tip.

    Is the part shown in the waveform above, passing those tests ? ie the effect is non destructive, and not always the same current ?

    Does that part then work normally, when mounted on a PCB ?

    If the current varies, and tests pass ok, that rather excludes a fixed die fault, but suggests some init or sequence issue.
    What is the highest possible Analog mode pin current requirement eg if all DACs are enabled, at highest DAC drain ?
  • cgracey wrote: »
    Something's screwy. The biggest hint we have is that the test engineer said that the VIO base current changes each time he re-seats the test head. It's been as high as ~500mA! This may be a purely mechanical problem, with perhaps some metallic filament thrown in.


    A certain amount of over-travel is required after the first probe makes contact with the wafer, for two reasons:

    to guarantee that all probes have made contact (to account for non-planarity of the wafer)
    to break through the thin oxidized layer (if the metal pad is Aluminum) on the pad
    https://en.wikipedia.org/wiki/Non-contact_wafer_testing

    What if the VIO is shorted to VSS? Then some of the resistance would be from the oxide layer, which could vary. The rest would be from the probe, which I'd expect to be significant at 100s of mA.

    Would it be possible to test resistance of the VIO to GIO before applying power? Is a shorted VIO a probable defect?

    We could measure VIO to VSS resistance.

    I don't think there's any likelihood that they should short, but who knows?
  • cgraceycgracey Posts: 11,711
    edited 2019-08-14 - 06:08:54
    jmg wrote: »
    cgracey wrote: »
    So much current flows sometimes, that the VIO probe tip melts. The tester probably supplied its maximum current of 2A. A VIO pin can, at most, normally pass 200mA, in the case of its four I/O pins outputting highs while shorted to GND. It probably took several times that much current to melt that probe tip.

    Is the part shown in the waveform above, passing those tests ? ie the effect is non destructive, and not always the same current ?

    Does that part then work normally, when mounted on a PCB ?

    If the current varies, and tests pass ok, that rather excludes a fixed die fault, but suggests some init or sequence issue.
    What is the highest possible Analog mode pin current requirement eg if all DACs are enabled, at highest DAC drain ?

    "Yes" to all questions in the first two paragraphs.

    Yes, it seems like a test problem, not a die problem, because the new chip I have soldered onto a RevA P2 Eval board works fine, with no excessive VIO current.

    If all pins were configured as 75-ohm 2.0V DACs, outputting $FF, they would draw ~1.0A, or 65mA per VIO.
  • I don't know about making integrated circuits

    First power-up,

    How are the ram/registers content, after baking the dies?
    Random ?
    Do you first have to drop some code to get initial "normal" status of all the registers?

  • Yes Chip, you must go down there!

    Most of the time you’ll find something silly going on that you just cannot diagnose remotely.

    If they don’t want you down there immediately, might be they need to fix/tidy something their end. I’ve seen this sort of thing too. After all, they want to charge you $$$$ for all these failed pins, so they won’t want you to find fault with their equipment. While OnSemi have been great, doesn’t mean it isn’t their test setup.

    And take a flight if you can. It will work out cheaper in the long run.
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  • The es board has decoupling on all supplies...

    Maybe that is the key difference?
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  • Chip,
    Is there combinations in the core's control lines that could drive a pin both high and low at once?
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • evanh wrote: »
    Chip,
    Is there combinations in the core's control lines that could drive a pin both high and low at once?

    No. The interface to the pin from the core cannot set up dangerous combinations. The pin decodes everything internally. No funny stuff possible.
  • Ltech wrote: »
    I don't know about making integrated circuits

    First power-up,

    How are the ram/registers content, after baking the dies?
    Random ?
    Do you first have to drop some code to get initial "normal" status of all the registers?

    All the flipflops are reset by the RESn pin, while the RAMs need initialization from code.
  • Sounds as if there is either a misconfiguration of the test harness or the chips were manufactured with a couple of pins swapped. Seeing as how they work fine on the ES board, I suspect it is the former.
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  • ke4pjw wrote: »
    Sounds as if there is either a misconfiguration of the test harness or the chips were manufactured with a couple of pins swapped. Seeing as how they work fine on the ES board, I suspect it is the former.

    Yes, the test harness being wrong seems most likely.
  • There's just no substitute for showing up physically to solve a problem, regardless of the inconvenience it poses. When I was doing fruit sizers, I was called to visit a site where the apples were not exiting their proper trip points and falling off the end of the roller-chain conveyor. It became quickly apparent that the chain had stretched over time and that repositioning each exit solenoid accordingly would solve the problem. It was one of the few site visits that I was able to return home from the same day. But if I hadn't gone, the problem would've lingered without someone else figuring out the cause.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • jmgjmg Posts: 13,920
    cgracey wrote: »
    Yes, it seems like a test problem, not a die problem, because the new chip I have soldered onto a RevA P2 Eval board works fine, with no excessive VIO current.

    If all pins were configured as 75-ohm 2.0V DACs, outputting $FF, they would draw ~1.0A, or 65mA per VIO....
    All the flipflops are reset by the RESn pin, while the RAMs need initialization from code.

    So a random number (say 25%) of DACs enabled at 50% average, could possibly create a total Iio of ~125mA.
    - but those are going to be properly reset by RESn ? and I'd assume they drive RESn very early in the tests, and likely more than once ?


  • ON's test engineer ran some very simple tests today and it looks quite certain that the problem is on the dies, themselves.

    Each device exhibits different, but 5..20-ohm, resistances from VIO to GND, on at least one VIO pin. We don't know exactly which or how many VIO's are involved because their tester wires them all together. I will check our seven remaining glob-tops to see if there's a pattern. It might be something borderline that happens on some VIO's and not on others (or even on any, in some cases).

    Look at the plots below for old and new silicon. When VIO (all VIO's) rises on the new part, current remains directly proportional to voltage, even from 0V, so there's some resistor present that shouldn't be there. If this were an active component problem, we'd need to get to at least 300mV before we'd see any conduction. This happens from 0V.

    I think they are going to have to re-run this through the fab. Something got messed up. They are going to blind-build a bunch of chips (forego the wafer probing) and see what we've got. We need to measure resistance from each VIO to GND to find out if the fault is consistent. I suspect it will be, somewhat. It seems to me that either something got boogered up and metal went where it shouldn't have, or a metal fill pattern was placed in empty space and it wound up sometimes shorting VIO to VSS and/or GIO (probably VSS).

    Now, we must wait for ON to get these blind-build parts packaged. If it turns out that failures are consistently on certain VIO pins, we could build a bunch of P2 Eval RevB boards with those VIO pins broken off the package. So, you might loose some number of four-I/O-pin sets.

    Bummer.
    1928 x 1048 - 108K
    1928 x 1048 - 152K
  • At this point, there's no point in me going out to Pocatello where the testing is being done.
  • jmgjmg Posts: 13,920
    cgracey wrote: »
    Each device exhibits different, but 5..20-ohm, resistances from VIO to GND, on at least one VIO pin. We don't know exactly which or how many VIO's are involved because their tester wires them all together. I will check our seven remaining glob-tops to see if there's a pattern. It might be something borderline that happens on some VIO's and not on others (or even on any, in some cases).

    Very strange that was not on the first batch ? Could their stressed probes have been damaging die ?

    How many packaged parts do OnSemi have ?
    If this is Ohmic, they could use a simple multimeter to check each Vio ?
    If they cannot easily isolate VIO's, we have used millivoltmeters in the past to measure copper-trace drops, and those mV can indicate which pins are consuming current.

    Do you have a ZIF socket with GND PAD spring pins ?
    cgracey wrote: »
    Now, we must wait for ON to get these blind-build parts packaged. If it turns out that failures are consistently on certain VIO pins, we could build a bunch of P2 Eval RevB boards with those VIO pins broken off the package. So, you might loose some number of four-I/O-pin sets.
    Bummer.
    Bummer indeed. Will those be glob-top parts ?
    Even if it is not consistent, as long as the BOOT quad group ok, you can do some P2 testing.

  • cgracey wrote: »
    ON's test engineer ran some very simple tests today and it looks quite certain that the problem is on the dies, themselves.

    Each device exhibits different, but 5..20-ohm, resistances from VIO to GND, on at least one VIO pin. We don't know exactly which or how many VIO's are involved because their tester wires them all together. I will check our seven remaining glob-tops to see if there's a pattern. It might be something borderline that happens on some VIO's and not on others (or even on any, in some cases).

    Look at the plots below for old and new silicon. When VIO (all VIO's) rises on the new part, current remains directly proportional to voltage, even from 0V, so there's some resistor present that shouldn't be there. If this were an active component problem, we'd need to get to at least 300mV before we'd see any conduction. This happens from 0V.

    I think they are going to have to re-run this through the fab. Something got messed up. They are going to blind-build a bunch of chips (forego the wafer probing) and see what we've got. We need to measure resistance from each VIO to GND to find out if the fault is consistent. I suspect it will be, somewhat. It seems to me that either something got boogered up and metal went where it shouldn't have, or a metal fill pattern was placed in empty space and it wound up sometimes shorting VIO to VSS and/or GIO (probably VSS).

    Now, we must wait for ON to get these blind-build parts packaged. If it turns out that failures are consistently on certain VIO pins, we could build a bunch of P2 Eval RevB boards with those VIO pins broken off the package. So, you might loose some number of four-I/O-pin sets.

    Bummer.
    Ugh. Sorry to hear this.
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