Automated Testing of P2's

1567810

Comments

  • Ale wrote: »
    I want a board, even an old one.

    @Peter Jakacki still has some EVAL1 chips and need to mount them on P2D2s. Just bother him enough to solder them. I would want one too..

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • AleAle Posts: 2,356
    @Peter do you have some chips to solder ? we would like them, pretty please ?
  • Ale wrote: »
    @Peter do you have some chips to solder ? we would like them, pretty please ?

    Same here. Please, just tell me where to send my payment and address.
    In science there is no authority. There is only experiment.
    Life is unpredictable. Eat dessert first.
  • David Betz wrote: »
    cgracey wrote: »
    These are all glob tops. They are not as reliable as the Amkor packages, but they work.
    What are you going to do with these new boards? Maybe you should send one to ntosme2. He's making great progress on getting GCC working for P2.
    Second that! He should get a board.

    Kind regards, Samuel Lourenço
  • ON Semi has sorted the four virgin wafers that were never exposed to the V-Stress test. I think they should have at least 800 known-good dies from this effort. They are going to send them off to Amkor for packaging. We are waiting to hear how soon they expect these parts back.
  • Thats' great Chip!That means a lot of ES ver 2 boards can be out there. Now we need a suite of test programs to run them through the gambit.
  • cgracey wrote: »
    ON Semi has sorted the four virgin wafers that were never exposed to the V-Stress test. I think they should have at least 800 known-good dies from this effort. They are going to send them off to Amkor for packaging. We are waiting to hear how soon they expect these parts back.
    Wow! That's great news. I'm glad you were able to get some usable chips out of this spin. Have you decided yet if these will be the production chips or if you will respin to add the guard rings?
  • PublisonPublison Posts: 11,031
    edited 2019-09-10 - 22:12:25
    cgracey wrote: »
    ON Semi has sorted the four virgin wafers that were never exposed to the V-Stress test. I think they should have at least 800 known-good dies from this effort. They are going to send them off to Amkor for packaging. We are waiting to hear how soon they expect these parts back.

    What would be the timeline for getting chips from Amkor to Rocklin? These would still be considered Evaluation Sample?

    I would love to be able to put a couple on the 5-P2D2 boards I have left. Maybe some other people in North America would like a board. I can give up 4 bare boards. Send me a PM.
  • RaymanRayman Posts: 9,791
    edited 2019-09-10 - 22:21:02
    By "sorted", do you mean they ran the tester on them, but without the V-stress this time around?
    Or, are you just skipping the testing?

    I guess "known-good" means they passed the tester, right?

    BTW: Will they let you do a modified V-stress with a lower voltage?
    Prop Info and Apps: http://www.rayslogic.com/
  • Great news indeed :)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • cgraceycgracey Posts: 11,745
    edited 2019-09-10 - 23:38:47
    I just talked to one of the ON Semi bosses about moving things forward.

    After probing those four virgin wafers (running all the tests on them), it sounds like they have ~1,100 known good dies from the last wafer run and they are maybe all available for packaging. They are working with Amkor to get these packaged. These can feed our development and early-adopter efforts for a while.

    We talked about doing a respin vs. using what we've got. The only known problem is the 4.62V-stress survivability on VIO pins. That would be easy to fix, but require a respin. We still need to see what comes of the latch-up test they are going to perform. If the latch-up test is negative, we would need to do a respin and fix the V-stress issue, as well. I told him that we should know what to do in a month's time, since we are sending new-silicon P2 Eval boards out to several of you, and that should produce some useful feedback. If they can get us those Amkor-packaged chips soon, we could get a lot more input, as we'd be able to produce a lot more P2 Eval boards.
  • Rayman wrote: »
    By "sorted", do you mean they ran the tester on them, but without the V-stress this time around?
    Or, are you just skipping the testing?

    I guess "known-good" means they passed the tester, right?

    BTW: Will they let you do a modified V-stress with a lower voltage?

    Yes, they omitted the V-stress test.
  • P2D2s? Thanks for the reminder, I will jump on it today and let you know.

    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    P2 --- The LOT --- TAQOZ INTRO & LINKS --- P2 SHORTFORM DATASHEET --- TAQOZ RELOADED - 64kB binary with room to spare
    P1 --- Latest Tachyon with EASYFILE --- Tachyon Forth News Blog --- More
    paypal.png PayPal me
    Brisbane, Australia
  • What's the latch-up test? I don't recall a latch up issue...
    Prop Info and Apps: http://www.rayslogic.com/
  • This is wonderful news!

    I only have two questions for Chip:

    1). Who will take my credit card number... and;
    2). Why havent you shipped mine yet? :) :)

  • Rayman wrote: »
    What's the latch-up test? I don't recall a latch up issue...

    Latch-up testing hasn't been done, yet, but needs to be. It should have been done on the prior silicon, but was overlooked.
  • evanhevanh Posts: 8,056
    edited 2019-09-11 - 01:14:43
    Rayman wrote: »
    What's the latch-up test? I don't recall a latch up issue...
    It's to verify that there are no issues. It exercises the protection diodes on the I/O pins and ensures they are clamping rather than transistors conducting - which can go into a latch-up state that only a power down will release.

    One way to do a latch-up test is use an AC signal with a series resister or capacitor so that the I/O pin is pushed hard against the power/ground rails. If the pin stops changing between high and low then a latch-up has occurred.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • Peter JakackiPeter Jakacki Posts: 8,722
    edited 2019-09-11 - 01:17:27
    cgracey wrote: »
    Rayman wrote: »
    What's the latch-up test? I don't recall a latch up issue...

    Latch-up testing hasn't been done, yet, but needs to be. It should have been done on the prior silicon, but was overlooked.

    Is there some responsibility on ON's part in this regard so that they bear the greater part of the cost to respin it again? If they had tested it properly the first time you would surely have found and fixed it, maybe with less pain and mystery, and the current respin would be 100%


    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    P2 --- The LOT --- TAQOZ INTRO & LINKS --- P2 SHORTFORM DATASHEET --- TAQOZ RELOADED - 64kB binary with room to spare
    P1 --- Latest Tachyon with EASYFILE --- Tachyon Forth News Blog --- More
    paypal.png PayPal me
    Brisbane, Australia
  • cgraceycgracey Posts: 11,745
    edited 2019-09-11 - 04:57:12
    cgracey wrote: »
    Rayman wrote: »
    What's the latch-up test? I don't recall a latch up issue...

    Latch-up testing hasn't been done, yet, but needs to be. It should have been done on the prior silicon, but was overlooked.

    Is there some responsibility on ON's part in this regard so that they bear the greater part of the cost to respin it again? If they had tested it properly the first time you would surely have found and fixed it, maybe with less pain and mystery, and the current respin would be 100%

    They are certainly aware of all these issues. We need to see if the latch-up test reveals any further problems that might necessitate a respin. Then we'll know where we are at, exactly. They want to see this turn out successfully, same as Parallax.
  • jmgjmg Posts: 14,013
    Rayman wrote: »
    What's the latch-up test? I don't recall a latch up issue...
    The failures may be due to scr triggering ( which is effectively ‘latch up’) triggered by their test profiles. Evanh’s tests suggest pure over-voltage limit is looking ok for 3v3 devices.
    Ideally, someone other than OnSemi can trigger a failure to get a sense of how ‘field delicate’ P2ES2 parts are.
    ES1 parts did spawn a couple of VIO node failure reports.

  • jmgjmg Posts: 14,013
    evanh wrote: »
    ...

    One way to do a latch-up test is use an AC signal with a series resister or capacitor so that the I/O pin is pushed hard against the power/ground rails. If the pin stops changing between high and low then a latch-up has occurred.
    Not quite. I posted a spice latch up injector earlier, which drives the IO pins outside the rails quite hard - enough to inject >> 100mA.
    Above some currents the VIO-GND parasitic SCR triggers, and tries to crow-bar VIO to gnd.
    If that crowbar current is not limited, local damage can occur on the die.
    The latch up test would inject (high clamping) Pin current, whilst observing VIO voltage,current when supplied from a weak power source.
    It may also be possible to trigger an ESD parasitic SCR via dV/dT triggering.
    ( your tests seem to have better outcomes than OnSemi’s, all I can think differs is dV/dT ?)
  • evanhevanh Posts: 8,056
    edited 2019-09-12 - 04:28:16
    Okay, I've done a small amount of that on one pin at the end of my earlier testing. Probably not over 10 mA though.

    EDIT: And even that 10 mA was only briefly while lifting VIO from 0.0 Volts up to 5.0 Volts via the I/O pin.

    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
  • jmgjmg Posts: 14,013
    evanh wrote: »
    Okay, I've done a small amount of that on one pin at the end of my earlier testing. Probably not over 10 mA though.

    EDIT: And even that 10 mA was only briefly while lifting VIO from 0.0 Volts up to 5.0 Volts via the I/O pin.
    It does not need to have a large duration, sub 1us is probably enough, but it does need to be largish - hundreds of mA on a ‘good’ device.

    For the +ve clamp direction, you need to avoid raising VIO if testing the Pin SCR, so the inject dumps an already charged cap into the clamp diode, completing the loop via the VIO pin.
    You may be able to check VIO SCRs using the PCB inductance where a small (100pF+1R?) cap is dumped to elevate VIO. Such an impulse could occur via ESD event, and it will occur that a Pin discharge does elevate VIO as the diode clamps into the pcb impedance.



  • That's great news, Chip!

    However, I think it would be a safer bet to release this batch as prototypes and then opt for a respin, nonetheless. At least it would be sure to solve an eventual latch-up issue, if there is one.

    Kind regards, Samuel Lourenço
  • samuell wrote: »
    That's great news, Chip!

    However, I think it would be a safer bet to release this batch as prototypes and then opt for a respin, nonetheless. At least it would be sure to solve an eventual latch-up issue, if there is one.

    Kind regards, Samuel Lourenço

    I agree.
  • Chip,
    How much additional extra $$ would it be to respin the verilog? Just asking ;)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Cluso99 wrote: »
    Chip,
    How much additional extra $$ would it be to respin the verilog? Just asking ;)

    That would come to $80k.

    Just fixing the pad ring GDS would be about $50k or $60k, as this involves new masks and a wafer run.

    What do you have in mind?
  • Cluso99Cluso99 Posts: 15,459
    edited 2019-09-14 - 05:47:26
    cgracey wrote: »
    Cluso99 wrote: »
    Chip,
    How much additional extra $$ would it be to respin the verilog? Just asking ;)

    That would come to $80k.

    Just fixing the pad ring GDS would be about $50k or $60k, as this involves new masks and a wafer run.

    What do you have in mind?

    I wondered about another P2 variant while keeping the existing P2 on hold for the time being to see some results if there really is a problem.

    If so, and presuming that the die can be made smaller which would shave a little cost from the ultimate pricing, then here are some ideas...

    * 4 COGs and maybe 256KB HUB RAM and maybe only 32 Smart pins, and possibly only 32 I/O.
    Don't know if you could fit this in a smaller package or there is some setup costs already factored into the Amcor package.
    This would use less power, and a smaller die may give us even higher clock rates. And 4 cogs gives even faster hub access.

    Taking the above a little sideways...
    * 4 COGs plus 4 reduced COGs (more like just the instructions equivalent to a P1 COG)

    I know nothing you can do will increase the HUB RAM to 1MB. Would 750KB be an option? And what would we need to remove for this?

    Might COG 0 be able to have more LUT (for code) ???

    Another question...
    Does the dual-port LUT between adjacent cogs take space or restrict layout?
    As the biggest proponent of the shared LUT, the hub speed makes this far less important now. Is it now necessary, particularly in a smaller P2?

    Just some ramblings while I have a little time ;)

    Postedit
    And if/when there is a verilog update, can you please add an instruction to partially replace the P1 JMPRET instruction.
    Not having a JMPRET equivalent makes converting P1 PASM a nightmare. Need the JMP #S(9bit) and JMPRET D,#S(9bit).
    Pretty please :)
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • Cluso99 wrote: »
    cgracey wrote: »
    Cluso99 wrote: »
    Chip,
    How much additional extra $$ would it be to respin the verilog? Just asking ;)

    That would come to $80k.

    Just fixing the pad ring GDS would be about $50k or $60k, as this involves new masks and a wafer run.

    What do you have in mind?

    I wondered about another P2 variant while keeping the existing P2 on hold for the time being to see some results if there really is a problem.

    If so, and presuming that the die can be made smaller which would shave a little cost from the ultimate pricing, then here are some ideas...

    * 4 COGs and maybe 256KB HUB RAM and maybe only 32 Smart pins, and possibly only 32 I/O.
    Don't know if you could fit this in a smaller package or there is some setup costs already factored into the Amcor package.
    This would use less power, and a smaller die may give us even higher clock rates. And 4 cogs gives even faster hub access.

    Taking the above a little sideways...
    * 4 COGs plus 4 reduced COGs (more like just the instructions equivalent to a P1 COG)

    I know nothing you can do will increase the HUB RAM to 1MB. Would 750KB be an option? And what would we need to remove for this?

    Might COG 0 be able to have more LUT (for code) ???

    Another question...
    Does the dual-port LUT between adjacent cogs take space or restrict layout?
    As the biggest proponent of the shared LUT, the hub speed makes this far less important now. Is it now necessary, particularly in a smaller P2?

    Just some ramblings while I have a little time ;)

    Postedit
    And if/when there is a verilog update, can you please add an instruction to partially replace the P1 JMPRET instruction.
    Not having a JMPRET equivalent makes converting P1 PASM a nightmare. Need the JMP #S(9bit) and JMPRET D,#S(9bit).
    Pretty please :)

    We have a whole family of P2 chips planned. We just need to go through the process of making them with ON Semi.

    I don't think we can get to 1MB of RAM in this 180nm process. The die would just be too big, even with only 4 cogs.

    It would be really difficult to make reduced-complexity cogs or cogs with more memory. Adding JMPRET back in would be too complicated, I think. It pretty much is what it is, at this point.

    In the future, we need a smaller process to get the next set of gains.

    Here is the planned P2X4C2M40P chip:



    1126 x 1159 - 34K
  • What might be general interest is a package without a thermal pad. Given the v2 die power is now half the v1 die, thermally I suspect this to be viable with 4-cog package, say a 64 pin package with:
    32x I/O
    8x VIO
    8x GIO
    6x VDD
    6x VSS
    TES/RES
    XI/XO
    "We suspect that ALMA will allow us to observe this rare form of CO in many other discs.
    By doing that, we can more accurately measure their mass, and determine whether
    scientists have systematically been underestimating how much matter they contain."
Sign In or Register to comment.