2-lane MIPI camera interface with P2?

MIPI seems to be taking over camera module interfaces...

Be nice to be able to use the $10 Raspberry Pi cameras on Amazon...

From what I can tell the physical layer is actually just LVDS. There are $1 LVDS receiver chips like FIN1028MX that can turn this into a 3.3 V signal.
But, how to get this data into P2 when using 2-lanes?
Maybe that's not the big problem, the big problem is that (at least I think) the data is DDR, coming on both rise and fall of clock.
It would be nice if the Smart Pin sync receive mode could support DDR..
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Comments

  • What's the DDR sample frequency? Is the data path 8 bits wide?
  • RaymanRayman Posts: 9,716
    edited 2019-06-08 - 21:47:08
    Oops, I was looking at the pixel clock maximum of 92 MHz, thinking that isn't so fast.
    But, it occurs to me now that the LVDS/MIPI clock rate is going to be (bits per pixel) times that...

    Never mind, that was dumb.

    Fortunately, the regular digital video port (DVP) output is still supported in many of these cameras, including the $9 one from Amazon with the OV5647 chip.
    Just means using 8 pins for data instead of 2 or 4...
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  • I certainly don't think it is dumb.

    I am presently fixated on $5, 8 bit antiquarian designs, that work out of the box.
    BUT... the future is right around the... oops there it is now!!!

    It looks to me that the newer camera designs are dropping 8/10 bit ports.
    I have seen some newer ones with gobs of pixels and as few as a single LVDS lane. They are certainly pushing the limits:)

    A while back I looked at deserializer chips. I don't remember a good option being available, but it has been a while.

    If it is practical, I think it would make a HUGE amount of sense to design an add on board that has a couple of these chips on it...
    It is beyond me, but it certainly isn't beyond you!!!


    Sign me up for a couple.


    Regards,

    Rich

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