P2-ES maximum current

Hello P2-ers!

Did anyone record maximum current consumption on VDD (1V8) during experiments?

I recall seeing @evanh post something whilst running at 350MHz... around 880mA (from memory; I can't find that post at the moment)


Were there any other tests done, especially running P2 at full tilt?


I'm trying to gauge the maximum real-world current requirement, hopefully to size an LDO supply on that rail. I'll set up a test later, but it would be good to cross-reference what others have encountered.
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Comments

  • jmgjmg Posts: 13,560
    VonSzarvas wrote: »
    Were there any other tests done, especially running P2 at full tilt?

    Based on the numbers reported, I ran up a Cpd model, which gives these

    Vcc=1.8; Cpd=1.60n+8*83.33p;Fi=300M; Id = Cpd * Vcc * Fi + 5m Id = 1.228A
    Vcc=1.8; Cpd=1.60n+8*83.33p;Fi=350M; Id = Cpd * Vcc * Fi + 5m Id = 1.432A
    Vcc=1.8; Cpd=1.60n+8*83.33p;Fi=400M; Id = Cpd * Vcc * Fi + 5m Id = 1.636A

    Challenges of a LDO are going to be mostly thermal ?

    These do not include clocked IO numbers, which are an adder on the VIO currents.

    The next P2 may have higher Cpd as there is more logic, and the equations will get more complex with clock gating, if that works as hoped.

  • I don't think I've run more than 250 MHz and only used the USB supply.
    I think that might be limited to 500 mA, wonder if that's true...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmgjmg Posts: 13,560
    Rayman wrote: »
    I don't think I've run more than 250 MHz and only used the USB supply.
    I think that might be limited to 500 mA, wonder if that's true...

    I'm not sure what margins they have on the nominal 500mA rating spec, but 250MHz from CPd above, gives 1.025A on 1.8V rail.
    So a power budget split on present PCB could be like

    0.85*434m*5.0/1.8 = 1.02472A on 1v8
    0.90*(500m-434m)*5.0/3.3 = up to 90mA available on 3v3, to keep under 500mA

    a better SMPS could nudge those to

    0.91*406m*5.0/1.8 = 1.026A
    0.94*(500m-406m)*5.0/3.3 = up to 133.87mA available on 3v3, to keep under 500mA

  • evanhevanh Posts: 7,150
    edited 2019-03-05 - 00:25:03
    I measured 888 mA at 300 MHz. But that would have been mostly idle I'd guess. https://forums.parallax.com/discussion/comment/1464987/#Comment_1464987

    Here's some more measurements with eight cogs + cordic all running. Note, my shunt leads were not high quality. I wasn't able to reliably do 350 MHz due to dropping Vdd.
    1v8 VDD supply
     MHz |    mV     mA
    ====================
      10 |  1832     53
      50 |  1816    257
     100 |  1797    497
     150 |  1778    733
     200 |  1760    961
     250 |  1744   1174
     300 |  1728   1378
    

    PS: I measure the shunt at about 75 mOhm. That's excluding the connector to the header.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Von,
    The 1v8 rail is the one that totally doen't need an LDO. That's a big advantage of all the work Chip has done to separate the I/O supplies internally in the Prop2.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • evanhevanh Posts: 7,150
    edited 2019-03-05 - 01:37:14
    I suspect 350 MHz could potentially reach 1.8 Amps on Vdd.

    EDIT: And the finished Prop2, although far more dynamic, will possibly have an even higher maximum.
    EDIT2: On the other hand, the respin may not reach 350 MHz. The P2ES has problems around 360 MHz.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,341
    edited 2019-03-05 - 01:59:54
    evanh wrote:
    I suspect 350 MHz could potentially reach 1.8 Amps on Vdd.
    I really worry about stuff like this. That's 3.24 watts of dissipation on the 1.8V rail, so the chip is gonna run hot! My concern is that the requirement for dual power supplies and the power-hungriness of the P2 -- among other complexities -- will limit Parallax's market for this chip. How did we ever get to this point? The P1 is much more elegant and user-friendly, and still after 13 years, it addresses Parallax's presumed market for industrial and educational microcontrollers in spades. Sorry, but I really don't see a need for the P2 at all.

    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • jmgjmg Posts: 13,560
    evanh wrote:
    I suspect 350 MHz could potentially reach 1.8 Amps on Vdd.
    I really worry about stuff like this. That's 3.24 watts of dissipation on the 1.8V rail, so the chip is gonna run hot!
    Only if clocked at 350MHz ....
    My concern is that the requirement for dual power supplies and the power-hungriness of the P2 -- among other complexities -- will limit Parallax's market for this chip.
    Many other > 100MHz CPUs have dual supplies. FPGA's have many supplies.

    I can see your point, about dual supplies, which is why I worry somewhat about the BOM & PCB area consumed with the present smps blocks.

    How did we ever get to this point? The P1 is much more elegant and user-friendly, and still after 13 years, it addresses Parallax's presumed market for industrial and educational microcontrollers in spades. Sorry, but I really don't see a need for the P2 at all.
    That's fine, you can signal that, by not buying a single one :)
    Others will see a niche for the P2, in Test & Measurement, Sensors interfaces, R&D, HMI, Industrial control, etc...

  • Remember that's a seriously overclocked case. I've just tried leaving that running with periodic reporting and it doesn't last long before terminal start skipping character then not much longer and it stops reporting. So, yeah, the heating is a real factor in reliable operation at those speeds. I can still hold my finger on the package but it is hot.

    350 MHz is not a practical expectation.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • It is possible with active cooling.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • evanh wrote:
    I suspect 350 MHz could potentially reach 1.8 Amps on Vdd.
    I really worry about stuff like this. That's 3.24 watts of dissipation on the 1.8V rail, so the chip is gonna run hot! My concern is that the requirement for dual power supplies and the power-hungriness of the P2 -- among other complexities -- will limit Parallax's market for this chip. How did we ever get to this point? The P1 is much more elegant and user-friendly, and still after 13 years, it addresses Parallax's presumed market for industrial and educational microcontrollers in spades. Sorry, but I really don't see a need for the P2 at all.

    -Phil

    Phil, this will let you run 2,000 P2 chips concurrently at 360MHz for only $6.25 per chip:

    https://www.ebay.com/itm/40-C-30L-Recirculating-Chiller-TempStar-C40-30-Fast-Cooling-Solution/112955558482?hash=item1a4cad0a52:g:X7EAAOSwiUpa26~Y
  • Okay, Chip, since you've decided to engage me on the topic, if you can answer the following questions to my satisfaction, I'll be quiet. Namely these:

    1. What is the market vacuum that the P2 is poised to fill?

    2. What will be Parallax's strategy to fill such a vacuum?

    Somehow the P2 has to pay for itself. It can't just be a scratch for someone's itch. And it's not yet clear to me that it's more than the latter. Please elucidate me.

    Thanks,
    -Phil
    “Perfection is achieved not when there is nothing more to add, but when there is nothing left to take away. -Antoine de Saint-Exupery
  • cgraceycgracey Posts: 11,149
    edited 2019-03-05 - 07:47:16
    Okay, Chip, since you've decided to engage me on the topic, if you can answer the following questions to my satisfaction, I'll be quiet. Namely these:

    1. What is the market vacuum that the P2 is poised to fill?

    2. What will be Parallax's strategy to fill such a vacuum?

    Somehow the P2 has to pay for itself. It can't just be a scratch for someone's itch. And it's not yet clear to me that it's more than the latter. Please elucidate me.

    Thanks,
    -Phil


    1) The P2 market is inventors who are hamstrung with systems that don't afford them accurate real-time control. The only current solution is to employ FPGA's, but they are quite difficult to work with. P2 makes it easy to get cycle-accurate performance with good analog, all in one integrated system with tons of hardware and software concurrency.

    2) Get the chip done, demonstrate its power and ease of use through short videos, make lots of interesting things with it, get the idea across to people that the P2 is worthy of their time investment, as it will return functional dividends that they can't get anywhere else. Foster a good community of people who produce and share lots of applications and know-how.

    Something like that.
  • Phil! The Prop2 has the same base educational market as the Prop1. Ideally they can be merged into the same development tools.

    The Prop2 can go further in terms of applications for both education and industrial. Give it some of your time.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • Here's a screenshot of the same reporting code as above but at 100 MHz and powered solely from the PC-USB. I've purchased a new powered USB hub.
    pin_lat0131.PNG

    The three traces at the top are all configured to 200 mV/div with 5.0 volts at 2 divs from top.
    Orange is the USB connector side of F401.
    Green is USB switch side of F401.
    Blue is 5V_Common at an accessory connector.

    The large drop across F401 severely limits possible loading.
    640 x 480 - 11K
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • evanhevanh Posts: 7,150
    edited 2019-03-05 - 08:24:16
    The 3v3 VIO switchmode regulator is not happy, looks similar to the 5 volts above. Checking the 1v8 VDD, it's fine. Has a nice flat trace.

    I'm liking the new USB hub. It has individual power switch for each port.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • jmgjmg Posts: 13,560
    evanh wrote: »
    ..
    The large drop across F401 severely limits possible loading.
    Maybe that should be resized ? Or, if there is already a USB-load SW that manages current, is that needed ?
  • can confirm that F401 is gone, with a different usb switch setting the current limit.

    F401 added too much resistance after recovery from a surge, so the voltage drop not ideal. Surging is too easy with P2 power requirements, for anything but the simplest of demos at normal operating frequency. As you spotted.

    That said, the next P2 proto chips should have lower current requirements- which will also help the 'powered by usb' experience.
  • That input is 500 mA rated, so it's intended to be limited. 100 MHz sysclock should be only around 250 mA on the 5 volt suuply though.

    However, having seen the 3v3 ripple, I'm wondering if maybe it's doing bad things.

    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • VonSzarvas wrote: »
    can confirm that F401 is gone, with a different usb switch setting the current limit.
    Cool.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • jmgjmg Posts: 13,560
    VonSzarvas wrote: »
    can confirm that F401 is gone, with a different usb switch setting the current limit.

    F401 added too much resistance after recovery from a surge, so the voltage drop not ideal. Surging is too easy with P2 power requirements, for anything but the simplest of demos at normal operating frequency. As you spotted.
    Good to hear.

    VonSzarvas wrote: »
    That said, the next P2 proto chips should have lower current requirements- which will also help the 'powered by usb' experience.
    The Power should be more cog-linear, if that level of Clock gating made the cut, which would mean a finite supply can manage more MHz with 1-4 COGs, but the current with all 8 COGS operating, will be likely slightly higher due to more logic.

    Still missing I think, is the Clock gating needed to operate COGs at differing effective sysclk speeds.

  • evanh wrote: »
    However, having seen the 3v3 ripple, I'm wondering if maybe it's doing bad things.

    The ripple will be greater at light loads. Not helped if all the VIO jumpers are set to LDO mode, so the switcher won't have much load at all (just flash memory and the on-board LEDs that draw maybe 1mA each).
    If the switcher is not being used for VIOs, then adding a load resistor across VIO to GND somewhere would clean that up- something in the region of 70 to 100 ohm.
    The ripple itself is not so large to be an issue for digital experiments, but might be a contributor at startup that limits the USB power supply (ie. surge in current increases resistance of F401).

    With the wide hold/trip/tolerance range on protection components, there sure is a conundrum to get the most power from the USB port, so as to allow useful P2 experimenting, whilst also protecting the USB port!
    All the feedback really helps up dial that in.

    The next EVAL board will have a switcher for 1V8 and LDO's only for 3V3.

  • jmg wrote: »
    The Power should be more cog-linear, if that level of Clock gating made the cut, which would mean a finite supply can manage more MHz with 1-4 COGs, but the current with all 8 COGS operating, will be likely slightly higher due to more logic.

    Maybe, depending on what the I/Os are configured to be doing. Inputs vs Outputs essentially. (as I understand things, inputs will need clocking in, but outputs that have not changed will not)

    Another aspect is the start-up current... it should be much lower because the "idle" P2 won't be clocking every idle I/O.
    Not really an issue with the P2-AUX supply, but that will help a lot when powered by a PC.

  • VonSzarvas wrote: »
    (as I understand things, inputs will need clocking in, ...
    Those aren't significant, we're talking synthesised logic. It's a lot lower power than the pad-ring logic. That said, there is others in this category that are more active: Free running PRNG, CT counter, and input debounce clocks. CT may now even be a 64-bit bus all on it's own!

    I feel that upping CT to 64 bits was overkill.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • TubularTubular Posts: 3,585
    edited 2019-03-05 - 11:53:09
    New MP2223 chip with dual step down dc-dc switchers (3A and 2A). Simple 8 pin package. Add LDOs to get the final 3v3

    No power good signal unfortunately

    https://www.monolithicpower.com/en/products/dc-dc-power-conversion/switching-regulators/step-down-buck/converters/vin-max-14v-to-19v/mp2223.html
  • VonSzarvas wrote: »
    With the wide hold/trip/tolerance range on protection components, there sure is a conundrum to get the most power from the USB port, so as to allow useful P2 experimenting, whilst also protecting the USB port!
    When I was looking for the new hub to buy I read about USB 3.0 adding backwards support of 900 mA rating on all 3.0 sockets even if only connected at USB 1.x data rates. This could be made use of, although I don't know how to specify it in documentation.
    The next EVAL board will have a switcher for 1V8 and LDO's only for 3V3.
    Nice. And that'll free a lot of board space.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • jmgjmg Posts: 13,560
    evanh wrote: »
    I feel that upping CT to 64 bits was overkill.
    Perhaps, but the power impact is minimal, because only 32 more flops are clocked, and any extra CT bus lines toggle very slowly indeed.
    CT needed to increase above 32b, so the question was really did it need to go all the way to 64b.

  • jmgjmg Posts: 13,560
    Tubular wrote: »
    New MP2223 chip with dual step down dc-dc switchers (3A and 2A). Simple 8 pin package. Add LDOs to get the final 3v3

    No power good signal unfortunately

    https://www.monolithicpower.com/en/products/dc-dc-power-conversion/switching-regulators/step-down-buck/converters/vin-max-14v-to-19v/mp2223.html

    Interesting part, but not really stocked yet. 8-pin TSOT23 is not thermally ideal, as it lacks a cooling PAD, but the fets are well spec'd 70mΩ/50mΩ for Ch1, 100mΩ/60mΩ for Ch2, Low RDS(ON) Internal Power MOSFETs
    $1.06/2.5k

    TI have a broadly similar part, 4.5~18V 2A/3A TPS542941RSAR (QFN16 4x4mm) which does have PGood, and is similar $1.15/1k FETS are not quite as good.. 150 mΩ (High Side) and 100 mΩ (Low Side)

    Dual parts still have a price premium, relative to single SMPS eg compare above with the new AP3441SHE, 8-VFDFN Exposed Pad, does have PGood, is rated 3A (2.7V~5.5V) and is just $0.14603/3k
  • If the fets are that low an on-resistance, its the schottky diode that needs a thermal pad more.

    3A though 0.07 ohm is 0.21V, the schottky will be 0.5V or so...

    Its interesting they can get that low in an integrated MOSFET, most of the H-bridge and stepper
    chips bottom out around 250 to 200 milliohm (although spec'd for higher voltage of course).

    Of course at some point there will be GaNFET switchers, and these primitive silicon parts will
    be in museums! Even a lowly EPC2111 half-bridge with the right driver can do 16A at upto 10MHz and
    has 19 and 8 milliohm devices: https://epc-co.com/epc/Portals/0/epc/documents/datasheets/EPC2111_datasheet.pdf

    The combination of one of these GaN 1/2 bridges and a suitable driver/controller would be an awesome
    combination, don't know if anyone's thought to build DC-DC converter housekeeping into a GaNFet driver
    chip yet. GaN gate driving is specialist, the voltage limits are critical and asymmetrical and leakage currents
    are large compared to silicon devices. Just need to invent something superior to ferrite next!
  • jmgjmg Posts: 13,560
    Mark_T wrote: »
    If the fets are that low an on-resistance, its the schottky diode that needs a thermal pad more.

    3A though 0.07 ohm is 0.21V, the schottky will be 0.5V or so...
    There is no schottky diode any more, in modern synchronous rectifier output designs. The Low side FET above, replaces the schottky diode.

    Mark_T wrote: »
    Its interesting they can get that low in an integrated MOSFET, most of the H-bridge and stepper chips bottom out around 250 to 200 milliohm (although spec'd for higher voltage of course).
    Oh, they go much lower than that, still in small packages.
    eg the AOZ1269QI-02 is 23-QFN (4x4) and just 62c/3k. but specs 2.7~28V 12A 18mΩ high-side 8mΩ low-side
    The similar AOZ2261QI-15 is 49c.3k, and specs 2.7~28V 8A 26mΩ 12mΩ
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