P2 Eval PCB Revision

2

Comments

  • Thank You!
    Infernal Machine
  • samuellsamuell Posts: 323
    edited 2019-06-17 - 22:22:27
    Hi,

    Noticed a few things on the schematic that were suppressed for good, IMHO. If I understood correctly, now there is no option to choose between the 3,3V from the DC-DC converter, or from the local LDO dedicated to each IO bank. I think the 3,3V DC-DC converter was pretty useless anyway, for the degree of noise it added, especially when generating an analog signal. Now, the VIO voltage is always provided locally by LDOs, which is great (and a dissipated power of just 0.8W per LDO, absolute worst case, seems reasonable to me). And the SMD pin headers that represented a physical weak point on the board, and could ruin it if one is not careful, are gone too.

    Also, I love the 1.8V still being supplied by a DC-DC converter with external inductor. Not that new integrated stuff. Nice move!

    I like this new board. I'll buy one, for sure! I'm anxious to compare the new P2 with the old one, to see if I can run some programs without hiccups, and also to see where the limits are (if the bar is raised).

    Kind regards, Samuel Lourenço
  • Nice work

    What model are the 8 LDOs used for the VIO pins?
  • samuellsamuell Posts: 323
    edited 2019-06-18 - 01:03:43
    Tubular wrote: »
    Nice work

    What model are the 8 LDOs used for the VIO pins?
    This is just a guess. They seem to be the same as the ones used in the previous board, judging by the surrounding components in the schematic, and also by looking at the footprints in the layout. Unfortunately, the revised schematic doesn't have a BOM. By looking at the BOM in the original schematic, they should be NCP114AMX330TCG. Anyway, I might be wrong and VonSzarvas is the best person here to confirm this.

    Kind regards, Samuel Lourenço
  • jmgjmg Posts: 13,609
    VonSzarvas wrote: »
    jmg wrote: »
    Is there a SCH for this ?
    Here goes!
    Thanks. That seems to lack part codes for regulators / SMPS ? & it cannot text search ?

    Most changes look good, revised SMPS is much more compact, with PGood included.
    What is the purpose of D901 ?


    Can I suggest a dual-footprint choice for LDOs ?
    The OnSemi NCP187AMT330TAG looks good on paper.
    Pluses : OnSemi part, includes PGood and is much better thermally, and has better Line regulation, (40 µV/V & 2µV/mA) and lower 10Hz noise (similar elsewhere)
    Minuses: Slightly higher cost, (21c/3k) and OnSemi said 'released in May' when I asked.
    Final P2 designs are more likely to choose such a single, higher rated regulator.

    Another regulator to consider allowing a single instance option of, would be the LT3045-1.
    That's not 'low cost' but it does have stellar Analog specs, so it could indicate where the P2 Analog noise floor is.
    If tests cannot measure difference between LT3045-1 & (much) cheaper NCP187A (etc), then users know they are P2-limited.


  • Samuel is correct! Here's that BOM.
    1432 x 1924 - 192K
  • jmg wrote:
    .
    What is the purpose of D901 ?

    Protection due to exposed header, for example if 5v gets put there by accident.

    Vf helps LDOs a little, to reduce heat close to P2 at higher loads. Looking for an improved thermal footprint, to compare with the images Tubular (I think) did for RevA!
  • VonSzarvas wrote: »
    Samuel is correct! Here's that BOM.
    Thanks, VonSzarvas.
  • If you get a moment VonSzarvas, have a look at the LP5907. Its available in the same footprint, and has order of magnitude better noise spec vs NCP114

    Chip suggested they could just change the BoM, but I don't think it happened
    https://forums.parallax.com/discussion/comment/1451821/#Comment_1451821

    There might be better options out there, and ideally these things should be tried as datasheet info can only summise so much, but that seemed the most suited ldo I found with a first survey of whats available.

    There may also be an argument for 1.0uF rather than 4.7uF caps - the NCP114 datasheet does some good comparisons between using 1.0uF and 4.7uF and its effect on noise, at the same 2.8v output

  • VonSzarvasVonSzarvas Posts: 1,543
    edited 2019-06-18 - 13:45:11
    I'm sure we did look at that before- It does ring the bell.

    There were some trade-offs between the two parts.

    LP5907 has a lower max current, and we really wanted to spec. 30mA per pin and 100mA on the headers. I think in a product where the total potential load was known and controlled (ie. not having user-breakout-headers), then 250mA probably would suffice though. The NCP114 delivers >500mA before it shuts down.

    The LP has marginally worse line regulation and accuracy, in lieu of the noise figure.

    That said... Those noise graphs are recorded with 1206 caps. Those will have a huge impact on the results, when compared to smaller packages with much lower impedance. It's a shame they didn't repeat the measurements with smaller packages. We went with 0402 4.7uF to get the lower impedance, whilst still ensuring minimum 1uF capacitance when de-rated at V.


    That said- it's a good one to note. If the LDO noise becomes a limiting factor for P2's analog, then swapping out half the LDO's to LP5907 could be a neat way to compare 4 samples by I/O group. You've stuck it on my mind! I'll see what opportunities present themselves during build.
  • VonSzarvas wrote: »
    That said- it's a good one to note. If the LDO noise becomes a limiting factor for P2's analog, then swapping out half the LDO's to LP5907 could be a neat way to compare 4 samples by I/O group. You've stuck it on my mind! I'll see what opportunities present themselves during build.

    Yeah I think that would be the ultimate, load a variety of capacitors and ldos on each of the 8 sites, and run some sweep tests.

    Thanks for considering it.
  • YanomaniYanomani Posts: 850
    edited 2019-06-18 - 15:20:09
    Hi Tubular and VonSzarvas

    Apart many other other sources that discusses the subject, Maxim Integrated Tutorial 5527 (https://maximintegrated.com/en/app-notes/index.mvp/id/5527) does a good job explaining how and why capacitor composition, construction, size, footprint and rated voltage could affect its effectiveness and suitability to any aplication.

    And especifically (to VonSzarvas), when it comes to the actual BOM, the curves shows some interesting (and advantageous) arguments to help deciding between X7R (preferred) and Y5F types.

    Sure, since X7F X7R ones tend to cost a bit more, it can be a valid argument in the decision taking proccess, but P2 Eval boards are meant to promote a Parallax product, thus any other parts can be selected in order to help improve its performance and operational range.

    Once P2 is stabilished as a good alternative, able to satisfy the most demanding applications its design has targeted, we'll all gain enough experience to allow some freedom in the selection of the surrounding components.

    Hope it helps a bit

    Henrique
  • Thanks for sharing the reference.

    You'll be glad to know, Eval uses all xxR caps :)

    Generally, I think most Parallax products avoid xxV and xxF (etc..) caps these days.
    Perhaps some older designs had them in places where temp drift and/or capacitance value really wasn't a factor, and it made sense to use the lower cost part. Probably the price difference is also less of a factor now, compared to 10-15 years ago.


    Another great resource is the cap manufactures websites- they pretty much all include detailed graphs and data for each capacitor, at each size, capacitance and voltage.

    For example, I have these urls bookmarked:
    https://psearch.en.murata.com/capacitor/spec/smd/
    http://www.samsungsem.com/global/product/passive-component/mlcc/general-n-high-cap/index.jsp
    https://ds.yuden.co.jp/TYCOMPAS/ut/searcherMain



  • Thanks VonSzarvas, I've just bookmarked them here! :smile:
  • jmgjmg Posts: 13,609
    VonSzarvas wrote: »
    LP5907 has a lower max current, and we really wanted to spec. 30mA per pin and 100mA on the headers. I think in a product where the total potential load was known and controlled (ie. not having user-breakout-headers), then 250mA probably would suffice though. The NCP114 delivers >500mA before it shuts down.

    The LP has marginally worse line regulation and accuracy, in lieu of the noise figure.

    The new NCP187A I mentioned above, has noise similar, or better (at 10Hz) than LP5907 and has much higher peak current, much better line regulation, and includes a PGood pin.
    To me, that's a `better fit` for P2 designs - but you might need to talk to OnSemi about exact availability


    VonSzarvas wrote: »
    That said- it's a good one to note. If the LDO noise becomes a limiting factor for P2's analog, then swapping out half the LDO's to LP5907 could be a neat way to compare 4 samples by I/O group. You've stuck it on my mind! I'll see what opportunities present themselves during build.
    Anyone wanting to really push noise, should test using the LT3045-1, that has exceptionally low noise numbers, (but they do charge for the specs)
  • The NCP187 looks good on paper, but the document log says 'released for production' in 2011, and a couple of revisions in 2015 and 2016... nothing in digikey nor mouser. Where did you come across it, jmg?

    I guess we keep an eye out for it and apply or some early samples if possible.

  • jmgjmg Posts: 13,609
    Tubular wrote: »
    The NCP187 looks good on paper, but the document log says 'released for production' in 2011, and a couple of revisions in 2015 and 2016... nothing in digikey nor mouser. Where did you come across it, jmg?

    I guess we keep an eye out for it and apply or some early samples if possible.
    I think those 2011/2016 date tags are for the package-pasted info (DOCUMENT NUMBER: 98AON55829E PAGE 2 OF 2), not the NCP187 itself ?
    I have April Rev0 data, and June Rev 1 data
    June data looks to add 2 more order codes, for ADJ & 0.8V to the 1.2V and 3.3V
    A 1.8V version of this could be interesting for light-P2 users.

    I got this reply from ON Semiconductor Technical Support on 18 May, when I asked :

    Device NCP187AMT330TAG was launched to production from May 2019. I believe this device will be available soon at our distributors.
    Of course 'soon' is rather vague ;)


  • Ah ok. Well thats a better outlook then

    Am I right in saying normally these things appear on Mouser/Digikey well before stock is available? I've seen that with the FPGAs. Not so sure about LDO regs
  • jmgjmg Posts: 13,609
    Tubular wrote: »
    Am I right in saying normally these things appear on Mouser/Digikey well before stock is available?
    Yes, that's common where they enter the part codes when they order the parts, and often show a lead-time.
    Sometimes they tag 'factory stock'.

    Digging more, I see this one has 'samples' buttons active (I think NCV8 is Automotive process/admin version so costs a few cents more) This part series do show 1.8V and coice of 2x2 or 3x3 packages
    https://www.onsemi.com/PowerSolutions/product.do?id=NCV8187
  • Ok. How about the lower spec (700mA) NCP167?
    https://www.onsemi.com/pub/Collateral/NCP167-D.PDF
  • jmgjmg Posts: 13,609
    Tubular wrote: »
    Ok. How about the lower spec (700mA) NCP167?
    https://www.onsemi.com/pub/Collateral/NCP167-D.PDF

    That has worse PSRR at low Freq, better at 100K and worse at 1.5MHz, but the noise looks to be far worse.... also has no PGood pin.
    You would think they could find `one good recipe` and use that ? ;)
  • Hi VonSzarvas

    Is the 64000-ES_REVB project closed, or there are still any mods planned to be implemented?

    I'm asking this, because, if not yet set on stone, I would like to know if someone (other than myself) could see any advantage in having some extra-connection means (at least the footprints, even at pcb's bottom side), to enable a 50 Ohm-impedance, external-clock signal to be fed to XI, running thru a capacitor and, perhaps, having series and parallel resistors too (termination/impedance match), don't forgetting some good GND connection?

    I'm wondering if some U.FL-R-SMT footprint could be designed at the top layer, since this kind of connector uses the least board space and its height (assembled and with a cable connected) would not interfere with anything else, if properly positioned (towards board's bottom-right, near the "propeller.parallax.com" graphism ???).

    Henrique
  • Yanomani wrote: »
    Hi VonSzarvas

    Is the 64000-ES_REVB project closed, or there are still any mods planned to be implemented?

    It's closed this time round. I just pasted your idea to the feedback doc for future revs. There might be some edits possible, when the chip goes from Engineering Sample to Productions release.

  • Thanks VonSzarvas.

    I have a trend to consider every fab run as the final one, but sure, you are right, there is one more stage to consider, even if there would be no more mods necessary at the silicon.
  • jmgjmg Posts: 13,609
    VonSzarvas wrote: »
    It's closed this time round. I just pasted your idea to the feedback doc for future revs. There might be some edits possible, when the chip goes from Engineering Sample to Productions release.

    Do you already have the suggestions for (VC)TCXO in the feedback docs ? :)

    The P2-Eval is rather sparse on clocking choices, for an Eval Board.
    I see P2 as very usable as an instrumentation platform, and the Eval board could drop into labs as semi-dedicated instruments.
    Those types of measuring are going to need `better than basic crystal` precision, and (VC)TCXO parts are quite low cost these days, thanks to GPS volumes.
    P2D2 has footprints for CMOS and Clipped sine, and on P2D2Pi, I've bumped the footprint choices to include Murata 200ppb models, and added a bridge to a DAC pin to control the VC, should someone want to externally lock to better than 200ppb.
    The cost in this is only PCB footprints.


  • samuellsamuell Posts: 323
    edited 2019-06-20 - 23:59:06
    Yanomani wrote: »
    ...
    I'm asking this, because, if not yet set on stone, I would like to know if someone (other than myself) could see any advantage in having some extra-connection means (at least the footprints, even at pcb's bottom side), to enable a 50 Ohm-impedance, external-clock signal to be fed to XI, running thru a capacitor and, perhaps, having series and parallel resistors too (termination/impedance match), don't forgetting some good GND connection?
    ...
    If I recall correctly, the terminations are done by the P2 itself, and no external resistors are needed. Any way, you have plenty of frequency combinations to choose from with a single crystal frequency. The dividers and PLL allow a vast number or clock speeds.

    Plus, an external connector might stop the crystal from oscillating.

    Kind regards, Samuel Lourenço
  • jmgjmg Posts: 13,609
    samuell wrote: »
    If I recall correctly, the terminations are done by the P2 itself, and no external resistors are needed.
    The P2 does not have 50 ohm style termination resistors, and certainly not on the Xtal pins.
    samuell wrote: »
    Any way, you have plenty of frequency combinations to choose from with a single crystal frequency. The dividers and PLL allow a vast number or clock speeds.
    ..for some values of 'vast'. However, even with the set of valid PLL integers, Xtal precision is quite poor, on the frequency quality scale.

    Yanomani wrote: »
    ... advantage in having some extra-connection means (at least the footprints, even at pcb's bottom side), to enable a 50 Ohm-impedance, external-clock signal to be fed to XI, running thru a capacitor and, perhaps, having series and parallel resistors too (termination/impedance match), don't forgetting some good GND connection?
    If the external signal manages 3v3 swing into the termination, a CAP would not be needed, but a series cap here is a good idea as it tolerates lower drives.
    I've found a clipped sine (typ 1v-pp-pp) AC coupled (330pF~1nf) into XI, is fine at 26MHz, and still works at 38.4MHz


  • YanomaniYanomani Posts: 850
    edited 2019-06-21 - 03:47:15
    I was thinking about the inclusion of the capacitor as a means to ensure better coupling/DC-offset isolation of, says, an externally originated master clock signal, comming from another PCB, and not necessarilly sharing the same 3.3 V regulators (e. g., lower voltages, if needed), but, sure, sharing a good GND interconnection.

    I was also stimulated by musing about any eventual demands msrobot's thread contents: "Streamer Questions - how to sync" could impose, when the ideas there expressed would be transported to any multiple P2-enabled designs.
  • VonSzarvasVonSzarvas Posts: 1,543
    edited 2019-06-21 - 05:17:54
    jmg wrote: »

    Do you already have the suggestions for (VC)TCXO in the feedback docs ? :)

    Yes. :)

  • VonSzarvas wrote: »
    jmg wrote: »

    Do you already have the suggestions for (VC)TCXO in the feedback docs ? :)

    Yes. :)

    Jmg,

    We should have made a land pattern on the PCB to accommodate a clipped-sine oscillator, but we didn't remember to. Next time, though.
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