P3 ideas

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  • jmgjmg Posts: 14,144
    Maybe P3 needs Phase-Change memory ? - looks like MRAM has been skipped over... ?

    https://www.st.com/content/st_com/en/about/innovation---technology/PCM.html
    https://www10.edacafe.com/nbc/articles/1/1651034/STMicroelectronics-Introduces-Safe-Real-Time-Microcontrollers-Next-Generation-Automotive-Domain-Architectures

    Impressive parts, " six Arm Cortex-R52 cores clocked at 400MHz, 16Mbytes of PCM, and 8Mbytes of RAM, all in a BGA516 package." plus "three Arm Cortex-M4 cores with a floating-point unit and DSP extensions to provide application-specific acceleration."

    They've used RAM here to run the code, (same as P1/P2/P3?) and use PCM as the boot-storage.
  • evanhevanh Posts: 8,382
    edited 2019-02-23 - 22:38:41
    PCM is an alternative to Flash. Both wear out on writes. Density is the priority. Its advantage over Flash will be speed.
    MRAM replaces DRAM - also a speed advantage, and large block SRAM in places like CPU caching or embedded main memory. MRAM can perform all functions only when highest density isn't important.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • New memory type are a matter of what OnSemi can offer, at what feature size, and at what royalty cost.

    Currently OnSemi seem to not offer Flash or eeprom for the P2, so what hope is there for the cutting edge technology?

    What I see as more interesting is the 1T or 1.5T RAM cells. Thats a huge silicon saving if they can get it mainstream - but again, at what royalty cost?
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
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  • I don't think JMG was thinking Prop3 really. I certainly wasn't replying in that fashion.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • jmgjmg Posts: 14,144
    Cluso99 wrote: »
    Currently OnSemi seem to not offer Flash or eeprom for the P2, so what hope is there for the cutting edge technology?
    OnSemi can do Flash and EE, but those need more process steps, so add to the price, and worse, they are slower than SRAM.
    To get the better MHz speeds, most vendors are going to loaded-RAM, and the smaller processes mean the cost of that RAM is at least tolerable.
    I've seen others offer stacked die, where a common/vanilla/low cost SPI flash part is 'inside the plastic'.
    Cluso99 wrote: »
    What I see as more interesting is the 1T or 1.5T RAM cells. Thats a huge silicon saving if they can get it mainstream - but again, at what royalty cost?
    Are those fast SRAM cells, or DRAM ?

  • It'd be nice to have jpg and mp3 encode/decode ability in real time...

    Maybe we do already with P2, not sure yet...
    Prop Info and Apps: http://www.rayslogic.com/
  • jmg wrote: »
    Cluso99 wrote: »
    Currently OnSemi seem to not offer Flash or eeprom for the P2, so what hope is there for the cutting edge technology?
    OnSemi can do Flash and EE, but those need more process steps, so add to the price, and worse, they are slower than SRAM.
    To get the better MHz speeds, most vendors are going to loaded-RAM, and the smaller processes mean the cost of that RAM is at least tolerable.
    I've seen others offer stacked die, where a common/vanilla/low cost SPI flash part is 'inside the plastic'.
    Cluso99 wrote: »
    What I see as more interesting is the 1T or 1.5T RAM cells. Thats a huge silicon saving if they can get it mainstream - but again, at what royalty cost?
    Are those fast SRAM cells, or DRAM ?
    Chip implied that Flash/EEPROM were not offered, not that there were additional process steps.
    As for speed, the flash/eeprom could be serial loaded as they are now so that's not necessarily an issue.
    Personally, I couldn't see why a 24C256 couldn't have been added to the P2 die as it is made by OnSemi in the same Onc18 process. Cost didn't seem to be the issue here.

    IIRC they are touting the 1-1.5T RAM cells as DRAM & SRAM replacements - they are static.

    What I'd really like to see is the SRAM stacked in layers on top of the cpu layers. More production cost for sure but it's all relative to what's inside :)
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • I get the impression that layer count is a major issue for cost. So when Chip said something wasn't available he probably meant not within the minimum number of layers.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • MRAM could excel as primary capture memory in digital storage scopes. 64 MB is a nice manageable amount that should fit on the same die along with management/display processor, sampling buffers and filtering compute units. No need for giant external SDRAM bus with its need for masses of SRAM buffers.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • jmgjmg Posts: 14,144
    Some very recent MRAM news from intel is here
    https://www.extremetech.com/computing/286084-intel-confirms-its-22nm-finfet-mram-is-production-ready
    https://www.tomshardware.com/news/intel-stt-mram-mass-production,38665.html

    Still not shipping in mass-market MCUs, and Toms link has 'weeks' in the retention without power column for MRAM, plus a finite read ceiling ?
  • Might just be ready for P4 in about 20 years ;)
    My Prop boards: P8XBlade2 , RamBlade , CpuBlade , TriBlade
    P1 Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    P1: Tools (Index) , Emulators (Index) , ZiCog (Z80)
    P2: Tools & Code , Tricks & Traps
  • JMG, those numbers on Tom's are stupid. It has DRAM and Flash at the same density!
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • In terms of density, they're making ground. Everspin has announced 1 Gb parts at 28 nm process (presumably by Global Foundries). Which compares as not too far off the common 8 Gb DRAM parts in PCs.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • I guess SLC Flash possibly is similar density to DRAM. But Flash moved on from those days maybe 20 years ago. With limited number very slow power hungry writes, density is king.
    We have the vastness of the internet and yet billions of people decided to spend most of their time within a horribly designed, fake-news emporium of a website that sucks every possible piece of personal information out of you so it can sell it to others. And they see nothing wrong with that.
  • RaymanRayman Posts: 9,936
    edited 2019-08-02 - 20:58:34
    I guess we don't have worry about derailing the P2 progress by suggesting things now...

    A post in P1 forum about a bad ENC28J60 driver got me wondering if it should be possible to put limits on what a driver cog can do.
    Maybe limiting access to certain pins and parts of HUB RAM would be a good idea...
    Prop Info and Apps: http://www.rayslogic.com/
  • Like a mask for DIRx that could be passed into the cognew?
    Memory protection would prob. require an MMU of sorts to be flexible enough.
  • potatoheadpotatohead Posts: 9,919
    edited 2019-08-02 - 22:19:37
    evanh wrote: »
    Chip! HDMI does't have analogue. You could call it full-HD video I guess.

    EDIT: I wonder if component video on TV's might handle that. I note my cheapo TV doesn't have component video inputs.

    Component TV officially goes to 1080i. Many take 1080p anyway.

    3 pins, optionally just one for grey scale monochrome! This is my personal favorite. Super lean on resources, high performance.

    I have yet to do it, but one can clock color at a different rate. Maybe save RAM.

    It may make sense to send analog into an HDMI chip for high resolution use cases.

    Analog sets allow you to play all kinds of games with the pixel clocks and resolutions. And it's all pixel perfect. Digital sets, given a stable signal, work really well at the various standard resolutions.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
  • For the Prop 3, I just want what could've been offered years ago in Prop 1.5: more counters per cog and more counter modes. Maybe higher speed. Don't even want more pins. Just that sweet, simple elegance of the Prop 1 architecture that makes programming such a pleasure!

    -Phil

    Yes, that would be the perfect P3 - If ever done - for a 110nm process.

    But why on earth are we even thinking about something new?
    I can hardly sleep while dreaming about some 4 cogs variants of P2 on 44-PLCC and 48-TQFP/64-TQFP.
    ... or a 2 cogs version in 32-TSOP/48-TSOP
  • MJBMJB Posts: 1,135
    edited 2019-08-04 - 17:44:43
    Ramon wrote: »
    For the Prop 3, I just want what could've been offered years ago in Prop 1.5: more counters per cog and more counter modes. Maybe higher speed. Don't even want more pins. Just that sweet, simple elegance of the Prop 1 architecture that makes programming such a pleasure!

    -Phil

    Yes, that would be the perfect P3 - If ever done - for a 110nm process.

    But why on earth are we even thinking about something new?
    I can hardly sleep while dreaming about some 4 cogs variants of P2 on 44-PLCC and 48-TQFP/64-TQFP.
    ... or a 2 cogs version in 32-TSOP/48-TSOP

    yea - those smaller (and cheaper) ones would make great super powerful real-time IO-Co-Processors with their SmartPins.
    Don't know how we would like memory to scale with less COGs. Keep it / reduce it ...
    I am sure there are applications for both - so find the right mix.

    but now let's play with the BIG one ... :-)
    waiting for P2D2 (new) plus dev board from Peter ...
  • Maybe it would be nice to have a switch that would prevent cogs from being restarted.
    That way, one cog could function as a supervisor and couldn't be restarted by bad code....
    Prop Info and Apps: http://www.rayslogic.com/
  • Maybe a privileged mode vs. user mode thing, seperate for each cog. In user mode, cogs can't stop other cogs, can't start cogs with access to pins that the starting cog doesn't have, can't change clock or hub settings.
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