This is pretty neat... Layout of P2Eval board forced me to think about how to use less pins.
I thought I'd try 3 octal D flip-flops... Thanks to jmg for thinking of the FIFO arrangement with shared latch pin and also that only need 2 octal flip-flops as can drive 8 bits directly.
The design files are in this thread (maybe I shouldn't have started a new one, but wanted people to see this!):
At 250 MHz I have just enough time to get 60 Hz refresh and very close datasheet timings.
There's probably margin to work with a lower clock rate.
I ordered SSOP instead of TSOP flip-flip flops, so had to bend some pins to make it work..
Here's a couple photos and the P2 source code: