Decoupling

I was in a conversation with a design engineer for a fairly large international company a few weeks ago, and our conversation drifted toward supply line problems and in particular capacitors.

And he went on a major rant about the amount of decoupling needed by modern CPU's, and the difficulty of sourcing proper capacitors. Tantalum is a strategic material and other materials are distinctly inferior. He said the processor they are using in their current product, a 160 MHz single core with a lot of ARM-like features, requires 10 to 20 decoupling caps. He said that people making cheap stuff like toys and games would make their prototype, then start pulling caps until it stopped working, then put a couple back in. Making industrial devices which have to perform to spec he couldn't get away with that.

I bring this up because it seems like P2 is designed from the outset not to need that much decoupling. And that could be an important advantage for some applications.

Comments

  • 7 Comments sorted by Date Added Votes
  • We don't really know whats required yet. For the moment we have a cap on each VIO and VDD pin, which is 32 caps.

    The good news is many other passives can be eliminated, especially resistors, due to the dacs and what is now built into each smart pin

  • Seems like for a production design though you could only decouple the pins you're using, right? That's not an option on other CPUs.
  • FWIW, I think Chip's board hardly has any decoupling fitted :(
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  • Certainly for the VIO you could do that. They're in blocks of 4 pins.

    I wonder about the tantalum thing, though, certainly that was the case some years ago, but ceramics have come such a long way

  • Tubular wrote: »
    We don't really know whats required yet. For the moment we have a cap on each VIO and VDD pin, which is 32 caps.
    I think Peter even added a ferrite bead to the 1v8, to calm the switching regulator noise.
    P2 currently has Cpd ~ 1.6nF + 83pF/COG, so will have quite significant switching currents, and EMC should benefit from 4 layer board.

    VIO caps will be determined by the pin activity/loads.
    It may be that smaller caps are better for VDD decoupling ?
    eg see https://www.eetimes.com/author.asp?section_id=36&doc_id=1320354 etc

  • This is a good point, jmg.

    It would be easy to replace a bank or two with 10nF (perhaps || 1uF) and see whether this affects ADC noise at all
  • jmgjmg Posts: 12,618
    edited November 27 Vote Up0Vote Down
    Tubular wrote: »
    This is a good point, jmg.

    It would be easy to replace a bank or two with 10nF (perhaps || 1uF) and see whether this affects ADC noise at all

    Just looking at 22nF / 15nF / 10nF, I see price minimum is at 0402 or even 0201 packages, in 16V or 25V, and Samsung 15nF 0402 data shows a |Z| min at 80MHz & < 1 ohm 10~800MHz

    lowest price in (>= 0402) is EMK105B7223KV-F Taiyo Yuden 0.022UF 16V X7R 0402 $0.0036/10k
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