ADC Sampling Breakthrough

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  • Hold on there, Phil. I STILL believe!

  • cgracey wrote: »
    TonyB_ wrote: »
    cgracey wrote: »
    What about the DC problem of only having 6-bit resolution?

    I think the 64-tap window is not the best. Max value is only 64, ramp length 16 and plateau 32. Try this:
    a = 16: b = 0: m = 1
    

    Max value is 256, ramp length 32 and plateau 0. Max sum is over twice as big.

    That looks a little rougher than the Tukey64, but generates twice the filter value.

    The problem with all these windows is that we're only getting 6-bit performance, in the case of a 65-tap setup.

    Maybe we should just implement a Sinc3/32, staggered for samples every 16 clocks, and get really good 8-bit samples, in every case.


    I've been watching this thread like crazy but a lot of this is over my head tbf. That said, I think most will agree a hardware windowing function would be nice. I guess I understand where Chip is coming from wanting a really nice ADC but I think that a sample per clock is way overkill. I think getting really good 8 bit samples is a great target. DC to maybe a couple MHz?
  • We've done been chasin' fools gold here.

    Looking at Sinc3 now and trying to figure out what is possible.

  • cgracey wrote:
    Hold on there, Phil. I STILL believe!
    Well, keep the faith -- I guess -- but, “Faith is believing what you know ain't so.” - Mark Twain :)

    -Phil
  • evanhevanh Posts: 9,648
    edited 2018-12-21 - 01:29:35
    I haven't got any time to look at the discussion but resolution definitely has huge improvement with Sinc3.

    Here's a flat line from my old spreadsheet work: These values are all 256 bit-clocks per decimation sample - CHUNKLEN in the source code. The Sinc1 line is all you get with existing hardware. DC-Level is scaled up from 50000 NCO to roughly 24-bit to give Sinc3 comparative equivalent.
  • Well, I'd say 2nd order sigma-delta can do better than sample size..
  • Rayman wrote: »
    Well, I'd say 2nd order sigma-delta can do better than sample size..

    What do you mean?
  • Well, it can give more ENOB that 1st order given a sample size.
  • I've been reading a lot about this and it's really amazing to me that there's no good relationship out there between raw sample size and ENOB.
    It's as if:
    a: it's obvious, no need to explain
    b: It's our secret
    c: nobody knows...
  • RaymanRayman Posts: 11,076
    edited 2018-12-21 - 01:46:49
    I've seen a lot of plots like this (see below).
    Turns out the noise (in dB) is directly related to ENOB.
    If you use a second order sigma-delta, you can win. But, needs more hardware...
    (note: always keep Fd << Fs)
    817 x 471 - 21K
  • cheezuscheezus Posts: 295
    edited 2018-12-21 - 01:57:47
    Rayman wrote: »
    I've been reading a lot about this and it's really amazing to me that there's no good relationship out there between raw sample size and ENOB.
    It's as if:
    a: it's obvious, no need to explain
    b: It's our secret
    c: nobody knows...

    I'd hazard a guess that it's all dependent on the signal, as well as the different sources of noise and error introduced along the way. It really would depend on what kind of a signal you are measuring, and what you are measuring for right? I think in terms of audio. For example, 16/44.1k -16 bit CD quality sounds good. I really couldn't tell much difference when A/Bing between the "cd quality master" and the 24/96k ADAT. Granted, this wasn't Neve / Sennheiser equipment but still midrange professional studio gear. When I record digital audio today it's 24/48k. I'm not expecting the P2's ADCs or DACs to push into this range.

    I keep looking at the smartpin modes and wondering what's going to be the best way to track for pitch. I'm pretty sure that I could get the P1 to make a pretty good guitar synth (pitch to midi) but now I'm starting to see potential in a lot of projects that I thought were just too hard.


    Just my 2 cents.
  • TonyB_ wrote: »
    CMA(x,y,z) is a Sinc3 filter when x=y=z. There are only four taps:
    t0 = 0*x : t1 = 1*x : t2 = 2*x : t3 = 3*x
    ' or
    a = x: t0 = 0: t1 = t0 + a: t2 = t1 + a: t3 = t2 + a
    
    delt = t(t0) - t(t1) * 3 + t(t2) * 3 - t(t3)
    

    There are a couple of useful CMA(x,y,z) with sum=x*y*z = 2^N:

    CMA(8,8,8), length = 24, sum = 512
    CMA(16,16,16), length = 48, sum = 4096

    And a couple with sum ~ 2^N:

    CMA(10,10,10), length = 30, sum = 1000
    CMA(20,20,20), length = 60, sum = 8000

    Chip, have you tried CMA(16,16,16) or (20,20,20)? The biggest one that would fit is (23,23,23) but that would be just for testing the quality as the sum is ~75% of 16384.

    Some other thoughts:

    1. A second-order modulator would be a significant improvement. Is that not possible with rev B? A N-order modulator really requires a N+1-order filter but that's all right as Sinc3 is third-order.

    From ADC Architectures III: Sigma-Delta ADC Basics, p.9:
    By using more than one integration and summing stage in the sigma-delta modulator, we can achieve higher orders of quantization noise shaping and even better ENOB for a given oversampling ratio [than a first order modulator].

    2. Scope mode was always meant to write one byte per pin per clock, so if the ENOB is less than 8-bit what does it matter? Software could oversample the stored bytes to increase ENOB.

    3. There is something called chopping:

    From Chopping on Sigma-Delta ADCs
    Chopping is a technique that can be used to cancel offset voltages and other low frequency errors... The effect is to virtually eliminate any offset errors arising within the ADC, and, more importantly, to minimize any offset drift with temperature.
  • TonyB_, can a 2nd-order modulator be realized by using two RC filters in series, instead of just a single RC filter?

    I'm experimenting with Sinc2 filters and they look okay. I wonder if Sinc3 really does much more for our 1st-order modulator?
  • jmgjmg Posts: 14,383
    Rayman wrote: »
    Well, I'd say 2nd order sigma-delta can do better than sample size..

    So too can first order, as your own spread sheet results gave 10 bits from a 256 decimate ratio.
    The TI data for 2nd order suggests ~13.5 ENOB on a real device, (filter produces a 16b result, but the analog parts and noise limit ENOB).
    The AD7403 info gives DNL/INL numbers under 1 LSB at 16b, for a 256 ratio
  • jmgjmg Posts: 14,383
    edited 2018-12-21 - 02:37:28
    TonyB_ wrote: »
    1. A second-order modulator would be a significant improvement. Is that not possible with rev B?
    Not really, as the Analog part is full custom, and that's an all-layer change.
    Worse, it's not clear if the noise floor of the Analog input would improve at all, and the existing first order ADC modulator is able to reach the noise floor from the numbers thus far.
    The Sinc3 filter allows external ADCs to be used, and those have rather lower noise floors.

    TonyB_ wrote: »
    2. Scope mode was always meant to write one byte per pin per clock, so if the ENOB is less than 8-bit what does it matter? Software could oversample the stored bytes to increase ENOB.
    My feeling is that the scope-mode filter only needs to be good enough to match the P2 noise floor, it does not need to be better, as there is no external ADC connection to consider in that mode.

    Sinc3 filter can be better, than P2-ADC, & up to 16b seems logical, as the commercial parts that can connect to P2, expect a 16b Sinc3, in their data.
    This also gives a decent sps rate.

  • jmgjmg Posts: 14,383
    I think it's safe now to declare that the filtering methods discussed here cannot increase resolution beyond the natural scope of the sample size.
    That's not entirely true. See the TI / ADi data sheets & Rayman's spreadsheets tests.
    There really are no rabbits in that hat. However, they might still be useful for reducing noise, at the expense of settling time. Nonetheless, I still aver that this is best left to software, rather than trying to integrate some sort of filter into the hardware.
    Problem there is, the SW is simply too slow. The external ADCs, which can do better than P2's on chip ADCs, need sinc3 = 3 adders, every 20MHz clock edge.
    That's one of the reasons the sinc3 adder part is done in hardware. The difference part can be slower, and that is done in software.

  • jmgjmg Posts: 14,383
    cgracey wrote: »
    TonyB_, can a 2nd-order modulator be realized by using two RC filters in series, instead of just a single RC filter?

    I'm experimenting with Sinc2 filters and they look okay. I wonder if Sinc3 really does much more for our 1st-order modulator?

    A key element of sinc3, is it 'does much more' for those external ADC's - ie it is usable not only on the P2 ADC, but also on the many external ADC versions too.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,655
    edited 2018-12-21 - 03:02:22
    jmg wrote:
    I think it's safe now to declare that the filtering methods discussed here cannot increase resolution beyond the natural scope of the sample size.
    That's not entirely true. See the TI / ADi data sheets & Rayman's spreadsheets tests.
    I'm putting my trust in basic information-theoretic concepts, verified by Chip's DC test results. Not sure where everyone else's faith is coming from.

    Granted, the filters may produce the illusion of increased resolution, due to a decreased apparent step size in variable signals, but it's nothing more than an illusion. You can't extrapolate beyond the results Chip verified for a DC input to AC signals. That finding holds whether the input signal is changing or not. It's fine to say that high-frequency noise is reduced, or that the waveforms look (sound? Yet to be determined) smoother. But it's a mistake to claim that low-res data can be massaged into accurate hi-res results by filtering. Information theory just doesn't support it. And neither should anyone here.

    -Phil
  • How does this fancy filtering violate information theory? Of course, it isn't meaningful to sample the provided output every clock; I would guess that there's some sample period between half and all of one window length which would allow perfect reconstruction of the data. It's not like it takes 7 bits in and spits 8 bits out or something; the 70 bits of the window length, or the something like half of that which would allow perfect reconstruction, is well more than 8 bits. It takes in a large (but not as large) number of bits and spits out fewer higher-quality bits.
  • From an information theory perspective (or at least my perspective) given Phil's example of a DC signal, the bitstream would contain way more information then we ever need. When you insolate the "interesting" signal out of the conversion noise you will STILL have a noisy sample, but a lot easier for the software to manage.

    I think the unicorn in the room is a perfect resolution / precision / sampling frequency. I think the ADCs need to be classified further before we can understand what kind of PRECISION we can get from them. IMO the effect we are seeing from the windowing function, sync3 or whatever FILTER we are using is a reduction in jitter. This improves resolution and possibly precision, at the expense of increased settling time.

    I still don't see this as a waste of time because Chip is figuring things out. I think what he REALLY wants is FLASH ADC. That would take care of multi-bit sample per clock. Maybe when it's time for a 4 cog variant :smirk:

    But thinking about the case Phil gave, accurately measuring a static value and this seems more like a job for the dac comparator modes. But that all depends on the DACs and it doesn't seem like there's been much classification of those yet.
  • Roy ElthamRoy Eltham Posts: 2,866
    edited 2018-12-21 - 04:19:29
    I still want to know what an audio signal sounds like after going through this. I'm guessing it will actually be worse than just 6bit resolution pretending to be 8bit. I think it will change the sounds in easily detectable, by your ear, ways.

    Also, I don't mean the theoretical stuff based on existing ADC/DSPs that have these things sitting on better ADC hardware. I mean using the P2's ADC and then whatever filters you are using to make your pretty sine wave pictures on the scope.
  • Roy Eltham wrote: »
    I still want to know what an audio signal sounds like after going through this. I'm guessing it will actually be worse than just 6bit resolution pretending to be 8bit. I think it will change the sounds in easily detectable, by your ear, ways.

    Also, I don't mean the theoretical stuff based on existing ADC/DSPs that have these things sitting on better ADC hardware. I mean using the P2's ADC and then whatever filters you are using to make your pretty sine wave pictures on the scope.

    I'm willing to bet you're right. Playing audio through this filter is going to sound... Terrible. Still, it should make for displaying pretty pictures on a TV easier right? Chip is playing back the samples through a DAC but you could just as well plot the same data points in a file or on a monitor. It would be really interesting to see what these filters do with a different front end.

    The disconnect I'm having,

    IIRC the sample clock is actually 1/7 the sysclock but the filters are running at sysclock. I'm hoping that I'm wrong and the filter is running at the sampling clock rate.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 22,655
    edited 2018-12-21 - 04:41:31
    How does this fancy filtering violate information theory?
    By itself, it does not. Interpreting the output as a real increase in resolution beyond n, when the bit sample size is 2n does. You're just counting bits. How they're weighted when you count them does not increase real resolution. It's simply impossible.

    -Phil
  • cgraceycgracey Posts: 12,809
    edited 2018-12-21 - 05:03:14
    Can anyone say anything about Sinc2 vs Sinc3 filtering for our ADC bitstream? Both seem to work okay.

    Does Sinc2 filtering yield lower ENOB than Sinc3 for the same sampling period? Sinc2 is way less expensive in terms of logic.

    We can make a replacement scope mode which uses Sinc3 to generate an 8-bit sample every 8 clocks by maintaining two final integrators and diff sets. Lazarus666 was talking about doing something like this on Prop1.

    If we can get similar quality using Sinc2 filtering, we can an 8-bit sample every 4 clocks, due to the huge logic savings.

    So, what's the difference between Sinc2 and Sinc3, again?
  • jmgjmg Posts: 14,383
    cheezus wrote: »
    The disconnect I'm having,

    IIRC the sample clock is actually 1/7 the sysclock but the filters are running at sysclock. I'm hoping that I'm wrong and the filter is running at the sampling clock rate.

    Not quite, the sampling clock = SysCLK = Filter clock, but at the higher sysclk speeds which P2 runs, it gets a little optimistic to expect the Current Mirrors + Comparator + D-FF to close that loop in under 5ns,
    so there is a tendency to clump the data more, and that 7 was Chip's observation of the rough peak of those clumps.
    Plus, at those very high speeds the mV change on the cap is quite small per SysCLK, which makes it more prone to noise injection disturbing any single edge decision.
    Provided there is no net charge injection, those noise ripples on the sense point should cancel/average out.

  • Phil, what is wrong with my simulation here? forums.parallax.com/discussion/comment/1458520/#Comment_1458520 I'm feeding the simulated ADC with small steps like would be seen from the 8 bit DAC. The voltages are held for 1000 clocks, much longer than the length of the window function. It does appear to resolve steps much smaller than 1/64 of full scale.

    Even if you are right about the 6 bit limit for a length 64 window, we still need a window filter to eliminate the edge effects. Review page 1 again. A simple sum of 64 consecutive bits from real hardware is likely to more than 1 LSB of noise. Chip was showing the noise for a rectangular window to be 4 counts.



    -James
  • cheezuscheezus Posts: 295
    edited 2018-12-21 - 05:44:18
    jmg wrote: »
    cheezus wrote: »
    The disconnect I'm having,

    IIRC the sample clock is actually 1/7 the sysclock but the filters are running at sysclock. I'm hoping that I'm wrong and the filter is running at the sampling clock rate.

    Not quite, the sampling clock = SysCLK = Filter clock, but at the higher sysclk speeds which P2 runs, it gets a little optimistic to expect the Current Mirrors + Comparator + D-FF to close that loop in under 5ns,
    so there is a tendency to clump the data more, and that 7 was Chip's observation of the rough peak of those clumps.
    Plus, at those very high speeds the mV change on the cap is quite small per SysCLK, which makes it more prone to noise injection disturbing any single edge decision.
    Provided there is no net charge injection, those noise ripples on the sense point should cancel/average out.

    Thanks for clearing that up, I knew I had something wrong there. This is really starting to get interesting and i'm kicking myself for not buying a scope a couple months ago when I had the chance :|

    I don't really know if there is an increase in ENOB from sync2 to sync3 but if there is it couldn't be more than a bit right?

    *edit

    Assuming that there is an improvement in ENOB, and assuming we are going to be using a different front end to drive it.. You could take a sync2 and do the 3rd in software? And can we get a decent 16 bit sample rate??
  • cgracey wrote: »
    Here is a second order modulator. Third order modulators are tricky and you need to reduce the gains somewhat.

    ds-2nd-order.png
    'a=4 : b = 00 : m=32   '17-tap Hann window, t2 and t3 cancel out
    'a=4 : b = 08 : m=16   '25-tap Tukey window
    'a=8 : b = 00 : m=04   '33-tap Hann window, t2 and t3 cancel out
    'a=8 : b = 16 : m=02   '49-tap Tukey window
     a=8 : b = 32 : m=01.5 '65-tap Tukey window
    'a=8 : b = 48 : m=01   '81-tap Tukey window
    
    gx = 10 : cy = 540 : by = cy + 100 : ay = by + 100 : dy = ay + 50 : sy = dy + 50
    sparse = 10
    
    t0 = 0
    t1 = t0 + a
    t2 = t1 + a
    t3 = t2 + b
    t4 = t3 + a
    t5 = t4 + a
    
    topbit = t5
    
    print "taps",,t0,t1,t2,t3,t4,t5
    
    dim t(topbit)
    for x = 0 to topbit : t(x) = 0 : next x 'clear bits
    
    adin = 0
    adinta = 0
    adintb = 0
    adintc = 0
    inta = 0
    intb = 0
    intc = 0
    
    for iter = 0 to 9999
    
      for x = topbit to 1 step -1 : t(x) = t(x-1) : next x 'shift bits
    
      adin = 1/6 + ((4/6) * (iter/10000)) 'new ADC bit
      adinta = adinta+adin
      adintb = adintb+adinta
      adintc = adintc+adintb
    
    ' adinta for first order
    ' adintb for second order
    ' adintc for third order (currently not working)
      if adintb >= 1.0 then  
        adintc = adintc - 1.0
        adintb = adintb - 1.0
        adinta = adinta - 1.0
        t(0) = 1
      else
        t(0) = 0
      endif
    
      delt = t(t0) - t(t1)*2 + t(t2) - t(t3) + t(t4)*2 - t(t5)
    
      inta = inta + delt
      intb = intb + inta
      intc = intc + intb * m
    
      x = gx + iter/sparse
      if x = int(x) then
        line x, cy, x, cy - intc/8 'plot intc
        line x, by, x, by - intb   'plot intb
        line x, ay, x, ay - inta*2 'plot inta
        line x, dy, x, dy - delt*8 'plot delta
        line x, sy, x, sy - t(0)*8 'plot ADC bit
      endif
    
    next iter
    
    

    Saucy, this looks great, but isn't this demonstrating a 2nd-order ANALOG integrator modulator? The slope looks fantastic, anyway.

    What about the DC problem of only having 6-bit resolution?

    Yes, it is a 2nd-order analog modulator. I'd say that's too risky to do for the P2 respin. We might be able to build one for the P1. I tried breadboarding it, doesn't work.

    Can the P2 operate with an external integrator cap like the P1 does?
  • cgracey wrote: »
    Here is a second order modulator. Third order modulators are tricky and you need to reduce the gains somewhat.

    ds-2nd-order.png
    'a=4 : b = 00 : m=32   '17-tap Hann window, t2 and t3 cancel out
    'a=4 : b = 08 : m=16   '25-tap Tukey window
    'a=8 : b = 00 : m=04   '33-tap Hann window, t2 and t3 cancel out
    'a=8 : b = 16 : m=02   '49-tap Tukey window
     a=8 : b = 32 : m=01.5 '65-tap Tukey window
    'a=8 : b = 48 : m=01   '81-tap Tukey window
    
    gx = 10 : cy = 540 : by = cy + 100 : ay = by + 100 : dy = ay + 50 : sy = dy + 50
    sparse = 10
    
    t0 = 0
    t1 = t0 + a
    t2 = t1 + a
    t3 = t2 + b
    t4 = t3 + a
    t5 = t4 + a
    
    topbit = t5
    
    print "taps",,t0,t1,t2,t3,t4,t5
    
    dim t(topbit)
    for x = 0 to topbit : t(x) = 0 : next x 'clear bits
    
    adin = 0
    adinta = 0
    adintb = 0
    adintc = 0
    inta = 0
    intb = 0
    intc = 0
    
    for iter = 0 to 9999
    
      for x = topbit to 1 step -1 : t(x) = t(x-1) : next x 'shift bits
    
      adin = 1/6 + ((4/6) * (iter/10000)) 'new ADC bit
      adinta = adinta+adin
      adintb = adintb+adinta
      adintc = adintc+adintb
    
    ' adinta for first order
    ' adintb for second order
    ' adintc for third order (currently not working)
      if adintb >= 1.0 then  
        adintc = adintc - 1.0
        adintb = adintb - 1.0
        adinta = adinta - 1.0
        t(0) = 1
      else
        t(0) = 0
      endif
    
      delt = t(t0) - t(t1)*2 + t(t2) - t(t3) + t(t4)*2 - t(t5)
    
      inta = inta + delt
      intb = intb + inta
      intc = intc + intb * m
    
      x = gx + iter/sparse
      if x = int(x) then
        line x, cy, x, cy - intc/8 'plot intc
        line x, by, x, by - intb   'plot intb
        line x, ay, x, ay - inta*2 'plot inta
        line x, dy, x, dy - delt*8 'plot delta
        line x, sy, x, sy - t(0)*8 'plot ADC bit
      endif
    
    next iter
    
    

    Saucy, this looks great, but isn't this demonstrating a 2nd-order ANALOG integrator modulator? The slope looks fantastic, anyway.

    What about the DC problem of only having 6-bit resolution?

    Yes, it is a 2nd-order analog modulator. I'd say that's too risky to do for the P2 respin. We might be able to build one for the P1. I tried breadboarding it, doesn't work.

    Can the P2 operate with an external integrator cap like the P1 does?

    Yes, it can. The clocked feedback is all in the pin, too, so it doesn't have to go through a cog's CTR.

    So, is a 2nd-order modulator like what we've got, but with an additional RC stage, so that there are two in series?
  • cgracey wrote: »
    Yes, it can. The clocked feedback is all in the pin, too, so it doesn't have to go through a cog's CTR.

    So, is a 2nd-order modulator like what we've got, but with an additional RC stage, so that there are two in series?

    Glad to hear that. It would be sad to give up that capability for the convenience of an internal modulator.

    I imagine it would look like this:
             |-------|--digital out
            [R]     [R] 
             |       | 
    in--[R]--|--[R]--|--digital in
            {C}     {C} 
             |       | 
    gnd------|-------|--GND
    
    
    Omitting the caps to Vio.
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