Boot issue accessing SPI Flash after SD access

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  • I think the correct solution would be to use one more pin for SD CS and not use flash CLK. The main problem seems to be that the SD card sees CLK of the flash as CS.

    Mike
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  • jmgjmg Posts: 13,937
    msrobots wrote: »
    I think the correct solution would be to use one more pin for SD CS and not use flash CLK. The main problem seems to be that the SD card sees CLK of the flash as CS.

    Mike

    That is still a solution for anyone who wants to do that - they boot from flash, (or a small MCU) then can continue boot from any pins they like.
    The point of a SD boot choice, is to get another path 'for free' - importantly, one that does not cost, or disturb, any other pins.
  • msrobots wrote: »
    I think the correct solution would be to use one more pin for SD CS and not use flash CLK. The main problem seems to be that the SD card sees CLK of the flash as CS.

    Mike

    What! more pins for boot devices!! Heresy! .... and that's the problem. Not the problem that was and that has now been solved and besides the resistor ensures that both devices can operate regardless.




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  • Didn't Chip allow for 3-pin FLASH SPI? That would also solve the problem too.

    But, we do have a good solution anyway.
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  • jmgjmg Posts: 13,937
    Cluso99 wrote: »
    Didn't Chip allow for 3-pin FLASH SPI? That would also solve the problem too.

    But, we do have a good solution anyway.

    Not sure if that is still there, but smarter these days is probably to support an attempt at Fast Read DUAL IO - that costs no more pins, but flash boots twice as fast.
    All the recent Flash parts I looked at support these opcodes (Winbond, Adesto, SFMG FM25Q08)
    Table 7-3. Instruction Set Table 2 (Dual SPI Instructions)
    Instruction Byte                0       1        2       3       4       5
    Clock Number                    0 - 7   8 - 15   16 - 23 24 - 31 32 - 39 40 - 47
    Fast Read Dual Output           3Bh     A23:A16  A15:A8  A7:A0   Dummy   D7:D0 #1
    Fast Read Dual I/O              BBh     A23:A8#2 A7:A0   D7:D0.... #1 
    #1. Dual Output data: IO0 = (D6, D4, D2, D0), IO1 = (D7, D5, D3, D1)
    #2. Dual input address:
    IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0
    IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1
    
  • jmgjmg Posts: 13,937
    edited 2018-11-16 - 07:54:08
    ..and in today's news, more MRAM offerings...

    1Mb 108MHz 2.7V-3.6V AS201MA1G3B
    4Mb 108MHz 2.7V-3.6V AS204MA1G3B
    8Mb 108MHz 2.7V-3.6V AS208MA1G3B
    16Mb 108MHz 2.7V-3.6V AS216MA1G3B
    32Mb 108MHz 2.7V-3.6V AS232MA1G3B

    These parts also support command codes 3Bh, BBh shown above for Fast Read Dual I/O

    addit: they also mention this :

    9.2.37 JEDEC Hardware Reset : JEDEC Hardware Reset enables hardware reset to return the SPnvSRAM to default SPI mode.
    The JEDEC Hardware Reset protocol sequence is as follows:
    1. CS# toggles low to high to select the SPI device
    2. CLK remains in either high or low
    3. SI toggles high to low while CS# is going low. I/O [3:1] are Don’t Care
    4. CS# is driven high while SI remains low
    5. Repeat step 1 through 4 four times
    6. JEDEC Hardware Reset will occur after the 4th CS# is driven high
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