TOYF

Earlier I discussed my 65ISR design. Pretty quickly the major flaw was found, which is high interrupt-latency. I was already aware of that flaw.
I'm not very serious about the 65ISR as it is mostly an exercise in designing a super-tiny processor --- this is an uninteresting subject from the programmers' perspective --- writing programs in such a restricted environment (two 8-bit registers) is challenging, but not fun (somewhat like building a ship in a bottle).

I'm more serious about my TOYF design. This is a pretty powerful processor that should be competitive in the real-world for both price and performance (the 16-bit corner of the real-world, which is getting smaller every year as most people are upgrading to the 32-bit ARM Cortex).
The TOYF is pretty powerful, but it lacks interrupts, so you have to use a paced-loop. This can also be challenging and unfun. If you make your heartbeat fast enough that you don't lose any I/O data, you have to break up your bigger tasks into tiny pieces and do the pieces one per iteration.
There is a similarity here with the 65ISR in which the main-program needs to be punctuated by BRK instructions.

The TOYF is mostly for motion-control in which a paced-loop is typical anyway.
The TOYF is a VLIW processor loosely based on the MiniForth that I wrote the development system for when I was employed at Testra.
The TOYF only has 3 instructions per opcode, whereas the MiniForth had 5 --- but the TOYF can do addition in one instruction, which the MiniForth couldn't.

Comments

  • 10 Comments sorted by Date Added Votes
  • Do you mean this Testra: http://www.testra.com/ ?

    Are they still in business? Their website looks like something from 1998.

  • Heater. wrote: »
    Do you mean this Testra: http://www.testra.com/ ?

    Are they still in business? Their website looks like something from 1998.
    That is them.
    Here is info on Forth: http://www.testra.com/Forth/index.htm
    The MiniForth was built on the Lattice isp1048 PLD in 1994 when I was there. I wrote MFX. Since that time it has been upgraded to one of the Lattice FPGA chips, rewritten in VHDL, and the name changed to RACE. They still use MFX.
    The website doesn't look like it has been updated since the 1990s --- they don't put much effort into advertising.
    Both brothers are (according to my calculation) in their early 70s now --- they are semi-retired --- afaik, none of their kids were interested in the RACE, so they will take it to the grave with them.

  • I like their 90's website. Loads ultra fast and has the info you need, and no added noise.
  • Heater.Heater. Posts: 21,177
    edited October 18 Vote Up0Vote Down
    I think it's great too. I'd be tempted to put a bit of CSS in there to make it look nice though.

    I like the conclusion on their RACE processor page:
    Reconfigurable processors are computational devices with reprogramable logic and data paths, that can be adapted to the needs of an application. For many applications, reconfigurable hardware has a computation potential orders of magnitude faster than fixed hardware.

    " This project demonstrates that a practical reconfigurable micro-controller can be build using a PLD. The main disadvantage of current PLDs for this application, is the large number of pins used connecting them to the memory. If as little as 2K of internal memory was available, 28 fewer I/O pins would be needed, and the economic advantage of using a PLD as a reconfigurable processor would be much higher."
    I might never have imagined a CPU would fit in a PLD, not that I ever knew much about PLDs as there is a big gap in the programmable logic I have used between PALs in the early 80's and my current DE-0 Nano board.

    Anyway, it seems to have taken us long time to get there but now we have things like that the small, cheap, Lattice FPGA's that can hold a 32 bit CPU easily.
  • Heater. wrote: »
    I might never have imagined a CPU would fit in a PLD, not that I ever knew much about PLDs there is a big gap in the programmable logic I have used between PALs in the early 80's and my current DE-0 Nano board.
    Testra wrote their own HDL for the Lattice isp1048 PLD (described on their website). LDL (Lattice Design Language) was not capable of making a processor fit on a PLD --- this is why they were the only company to succeed at this --- it is no longer possible to write your own HDL, as the needed information regarding the internal workings of the FPGA is not available due to being proprietary.

    The MiniForth had an 8032 coprocessor on board. This was needed to pony up the MiniForth, as it couldn't just start executing code on power-up without some outside help. The TOYF might also need to be ponied up like this --- I haven't gotten into Verilog yet, so I don't really know the details of what is needed to make the TOYF run.

    Also, there wasn't room for a UART on the PLD because the MiniForth was taking up all the resources, so the 8032 did the communication with the desktop-computer and then fed this data to the MiniForth via a parallel port. The 8032 had 64MB (not a typo; that is 64MB not 64KB) of RAM so it could store multiple files of data. This was an issue because the MiniForth only addressed 64KW of data-memory (data-memory contained both data and the Forth threaded code), so the use of the 8032 for holding big data files alleviated the MiniForth from needing some kind of memory-banking system that would have been complicated and likely wouldn't have fit in the already over-packed PLD.

    Anyway --- I haven't worked for Testra in a long time, so I don't want to sound like a salesman for them.

    The TOYF doesn't have interrupts. It might work well as a coprocessor to another processor (presumably something bigger than an 8032 this time).

    The eTPU doesn't have interrupts either. It is used as a coprocessor to another processor --- my understanding of it is that it has a paced loop in which it polls I/O --- this is used in modern automobile computers, so there is a lot of I/O from all those sensors.
    I have not programmed the eTPU --- the car manufacturers obviously don't hire people like me --- the eTPU is just something that Walter Banks told me about.
    Heater. wrote: »
    Anyway, it seems to have taken us long time to get there but now we have things like that the small, cheap, Lattice FPGA's that can hold a 32 bit CPU easily.
    I don't think that a 32-bit processor is a good idea unless you have 32-bit data and/or hundreds of kilobytes of memory.
    The physical world hasn't changed since the 1990s (actually, hasn't changed in billions of years), so data is still 16-bit (actually 12-bit most of the time) --- I wouldn't really expect to see micro-controllers working with 32-bit data --- as for memory, the TOYF can address 64KW of data-memory and 32KW of code-memory, which seems like a lot to me.

    The real power of an FPGA is the ability to do things concurrently. I think a better design in many cases would be a dual-core system with 16-bit processors. The TOYF is marginally useful as a single-core system, but the lack of interrupts limits what it can do. As part of a dual-core system though, it could really shine --- it can have a pretty tight paced-loop --- the other processor can run the main-program that is less time-critical.

  • In both cases. both this discussion and the original one, regardless of what everyone else thinks, I, myself think you've got it.

    Search for homebuilt CPU via Google. There's a webring, or rather was, and there are plenty of good ideas in there, and great explanations on what to avoid. Or visit Homebrew CPU

    And if his last name makes any noisy responses, it is because he's the brother to the same fellow who launched the Open WRT movement, and got people who own them thinking about the software their NSLU2 devices ran.

    For my part, in his bibliography is a two part article which was in Byte magazine about thirty years earlier. I suggest you find those two and read them.
    Oh and this message is being sponsored by the Big Foot Mountain Watch club, they watch you and gain interest in ignoring people.
  • Oh yeah. There's lots of people out there designing and building their own processors. Just now I'm following Robert Baruch's LMARV build: A RISC-V processor you can see:



    The Magic-1is a classic. It's magic!

  • I have an upgrade on the TOYF design to now support interrupts. I only allow interrupts in places where there is no state to save and restore though, to make going in and out fast, but there may be a lot of interrupt latency --- they are primarily provided for non-critically timed IRQs such as a UART --- you are still going to primarily rely on a paced-loop.

    I also upgraded the design to boost the speed on common primitives. For example, FETCH is now one clock-cycle faster. Also, the logic operators working with flags on the data-stack are now faster. For me, tweaking the design to boost efficiency is interesting --- it is all about finding ways to do things in parallel that were previously done in sequence --- there are a limited number of instructions possible (without upgrading to an 18-bit opcode), so there are a lot of trade-offs in regard to which primitives will be fast, and which will have less efficient code.
    Heater. wrote: »
    Oh yeah. There's lots of people out there designing and building their own processors. Just now I'm following Robert Baruch's LMARV build: A RISC-V processor you can see:
    When I started a thread discussing my 65ISR design, Heater hijacked it to promote the RISC-V.
    When I started this thread discussing my TOYF design, Heater hijacked it to promote the RISC-V.
    I will never respond to anything that Heater says again --- I am done with him --- I like my TOYF design, and I have no interest in the RISC-V which is not innovative in any way, and I'm not going to waste my time arguing with RISC-V enthusiasts.

    Discussing the TOYF on the Parallax forum is really off-topic because it is not a Parallax product and is not going to become one (it is conceivable though that a RISC-V board will become a Parallax product, as the RISC-V is a hobbyist project and Parallax already caters to hobbyists with the BASIC Stamp).
    I ask that discussions of the 65ISR or TOYF be taken to the anycpu forum. It is moderated, so hijacking threads like this is not allowed. If somebody has an agenda, they can start a thread about it, but if nobody responds they can't hijack all of the other threads striving to divert those discussions to their own agenda.


  • Heater.Heater. Posts: 21,177
    edited October 25 Vote Up0Vote Down
    HughAguilar,

    My apologies, I did not mean to hijack your thread.

    My comment about the home built RISC-V was only a follow up to Buck Roger's "Search for homebuilt CPU via Google.". It was meant by way of encouragement, you are not alone and there are many people tackling home brew CPU designs of all kinds. I guess you know that already though.

    Clearly I did not express myself well. So I offer my apologies.

    I do have to disagree with your statements that the RISC V is not innovative, it certainly is. And that it is hobbyist project, it certainly is not, except when people like me tinker with it of course. I'd like to explain why but I can understand that you don't want to discuss that here.

    As it happens I'm interested in what you are up to with your design ideas. Please do continue to present them here. I'm sure others are interested as well.

    Have fun.
  • I have enjoyed the design discussion. Thinking about CPUs is often challenging and thought provoking.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
Sign In or Register to comment.