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...and what kind of USB performance could be achieved at 280MHz :-)
Still 12MHz ? - as that's the USB clock speed.
The next step of 480MHz is well outside P2 ability, but maybe someone will connect a HS-USB PHY to a P2 one day ?
It would be quite interesting to load the USB code, and ramp the SysCLK, and see how clk tolerant the USB code is. (FPGA tested at 80MHz)