ADC Noise

cgraceycgracey Posts: 9,528
edited October 11 in Propeller 2 Vote Up0Vote Down
No matter what mode I put the ADC in, for a 16-bit conversion, I get noise in the ~5 LSBs.

I output this noise onto a DAC, so I could look at it. It is not just hash, but a continuous noisy function. It wanders up and down. Not sure what causes it or if it can be remedied.

Here is a scope shot of it. I calculate that the peak-to-peak amplitude of this noise is ~1.6mV, or 3.3V / power(2, 16-5).

The noise amplitude stays about the same, no matter what frequency I run the chip at.


ADC_noise.jpg

Here is my program:
' 16-bit analog to digital

con	p =	0

dat	org

	hubset	##%1_000001_0000011000_1111_10_00	'enable crystal+PLL, stay in 20MHz+ mode
	waitx	##20_000_000/100			'wait ~10ms for crystal+PLL to stabilize
	hubset	##%1_000001_0000011000_1111_10_11	'now switch to PLL running at 250MHz

'	bmask	dirb,#15

	rep	#2,#16
	wrpin	softmod,i
	add	i,#1

	wrpin	##%100000_0000000_00_01111_0,#p	'adc on
	wxpin	##$FFFF,#p
	wypin	#0,#p
	dirh	#p				'enable counter

	setse1	#%01<<6+p			'se1 triggers on adc sample

loop	waitse1					'wait adc sample
	rdpin	i,#p				'get adc sample
'	setword	outb,i,#0			'output it to P47..P32
	setbyte	dacmod,i,#1			'output lower byte of sample to P31 DAC
	wrpin	dacmod,#31
	drvl	#31
	jmp	#loop				'loop

i	long	32

softmod	long	%0000_100001001_00_00000_0
dacmod	long	%10100_00000000_00_00000_0
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Comments

  • 134 Comments sorted by Date Added Votes
  • Is that bad? Seems about what you'd expect...
    16 bits is a lot...
    Prop Info and Apps: http://www.rayslogic.com/
  • Could this be your setup with not much decoupling, and long-ish power leads that are just clipped on from an external power supply?
  • We should be able to Goertzel-detect very low-amplitude frequencies buried deep in the noise. That's my hope, anyway. Need to do more tests.
  • Roy Eltham wrote: »
    Could this be your setup with not much decoupling, and long-ish power leads that are just clipped on from an external power supply?

    It could be. This was about the same performance I saw on the test chip, when running it on the FPGA board.

    The noise moves slowly. You can see 2 seconds' worth on the scope shot. What would have such a low time constant? I don't think it's the chip. It's encouraging to note that on nearly the 3rd vertical graticule on the scope shot, you can see the noise gets very tight briefly. This suggests that the chip will be able to resolve much better if we can get the infrastructural noise out of the situation.
  • Do you have a way to check for something like this noise pattern in your power supply output?
  • Can you hit it with a hair dryer, Chip?

    In 12 hours or so, we should be able to repeat this with OzPropDev on the fully decoupled p2d2
  • YanomaniYanomani Posts: 635
    edited October 11 Vote Up0Vote Down
    Wasn't that the same kind of noise that plagged early-stage Flip boards?

    Although, IIRC, on Flip boards the problem was related to a noisy voltage regulator.
  • Roy Eltham wrote: »
    Do you have a way to check for something like this noise pattern in your power supply output?

    Good idea. I will check. However, I don't think 1.6mV is going to look like much on my scope. I will try, though.
  • Also does the scope have an fft mode?
  • cgraceycgracey Posts: 9,528
    edited October 11 Vote Up0Vote Down
    I took a close-up picture of the ADC noise. This makes me hopeful. It appears that something external is causing this wandering, and it's quite continuous. If this can be resolved, it looks like the noise floor should drop to maybe 1 or 2 LSBs:

    ADC_noise_closeup.jpg
    1359 x 1075 - 226K
  • I checked the 3.3V VIO power supply and I can see that my setup is not that great, because I'm getting 100mV of 60Hz power-line noise! I need to find two AA cells to power the VIO from.
  • To rule out any possibility of your own code causing it (current consumption signature), try inserting a NOP between every instruction at the loop, and check if the noise steps "widens" in time, accordingly.
  • cgraceycgracey Posts: 9,528
    edited October 11 Vote Up0Vote Down
    I found two AAA batteries that I series'd to power the VIO with, but the noise was still the same. The board is still connected to the bench supply for the 1.8V VDD.

    That 100mV of noise on VIO was an error. I soldered these really low-quality SIP sockets onto my P2D2 and they cause me perpetual setup headaches.

    Anyway, I do see the rails coming from the bench supply wandering around like the noise pattern on the ADC does. The main noise is limited to ~10mV with ~50mV high-frequency hash.
  • Rayman wrote: »
    Is that bad? Seems about what you'd expect...
    16 bits is a lot...

    My thoughts exactly. Not because I have an explanation but I just happened to be reading up on the 16 bit ADS1100, last night and there was a comment that, for all intents and purposes, only 13 bits are useful.
    PropBASIC ROCKS!
  • Tubular wrote: »
    Can you hit it with a hair dryer, Chip?

    In 12 hours or so, we should be able to repeat this with OzPropDev on the fully decoupled p2d2

    I don't have any heat or cooling like that with me.

    That would be great if you could try this out, too. I suspect that if we could get quiet power, the noise floor could improve a lot.
  • Tubular wrote: »
    Also does the scope have an fft mode?

    Yes. The FFT just looks noisy, too, though.
  • Yanomani wrote: »
    To rule out any possibility of your own code causing it (current consumption signature), try inserting a NOP between every instruction at the loop, and check if the noise steps "widens" in time, accordingly.

    99.9% of the time is spent waiting in the WAITSE1 instruction.

    The noise I'm seeing is wandering around slowly.
  • Peter JakackiPeter Jakacki Posts: 7,709
    edited October 11 Vote Up0Vote Down
    I adjusted this so that my 12MHz oscillator switched the P2 to 250MHz just to keep it the same and I seem to get very similar waveforms. I will keep checking shortly. The 2nd trace is the 3.3V supply but all looks well on the 1.8V side too.

    MSO1104Z_DS1ZD180800127_2018-10-11_22.31.42.png
    MSO1104Z_DS1ZD180800127_2018-10-11_22.36.02.png

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  • Peter, thanks for checking that. It does look quite similar.

    Where are these long noise periods coming from? You can see that adjacent conversions are quite close, but they wander around over many samples.

    I wonder what kind of effect low-frequency power-supply noise has on the ADC.
  • Has dithering and the xoroshiro128** generator anything to do with this?
    Formerly known as TonyB
  • TonyB_ wrote: »
    Has dithering and the xoroshiro128** generator anything to do with this?

    Well, these pad circuits work entirely in the VIO domain, while all the xoroshiro128** activity is in the VDD domain, probably causing some noise, but maybe none that could affect the ADCs.
  • TonyB_ wrote: »
    Has dithering and the xoroshiro128** generator anything to do with this?

    I'm just outputting 8-bit DAC values without the smart pin dithering.
  • PropGuy2PropGuy2 Posts: 171
    edited October 11 Vote Up0Vote Down
    That noise is pretty low considering the long-ish hookup leads and working on a table that could bring in who-knows-what noise (florescent lights, for instance). I suspect you are not seeing everything in the noise department, been there and done that. Time to dust off the good old time ANALOG scope (400 MHZ is a good start) to get a grip on the noise problem...
  • Maybe you could use pins on either side to do active noise cancellation :)
    Prop Info and Apps: http://www.rayslogic.com/
  • Or, if there's no correlation between noise on other pins, you could use more pins to get more bits, right?

    Wonder how that would work... 1 bit for 2 pins, 2 bits with 4 pins?
    Prop Info and Apps: http://www.rayslogic.com/
  • cgracey wrote: »
    .

    That would be great if you could try this out, too. I suspect that if we could get quiet power, the noise floor could improve a lot.

    With a simple CMOS inverter element the PSRR will be a lousy 50%, so VERY CLEAN power & gnd would be needed.
    I would suggest clean linear local supplies, no PLL, and a lowish MHz external OSC that is mains cycle related, so you measure over a whole mains cycle to null residual inevitable hum sources.
    What is the integrator R,R,C ? (Keep sysclk high enough the integrator swings well, but does not clip.)

    I do not see quiet zones ? If you you draw a histogram of the next reading deviation, that is not full swing random, but appears more step-from-last related.
    That makes two adjacent equal readings more likely, so the ‘quiet’ may just be stats at work.
  • Ferrite cores around power leads?
    Ken N8SYG
  • I think I'd put an active probe on the input pin to see what's really there without affecting it...
    Prop Info and Apps: http://www.rayslogic.com/
  • cgraceycgracey Posts: 9,528
    edited October 11 Vote Up0Vote Down
    Rayman wrote: »
    I think I'd put an active probe on the input pin to see what's really there without affecting it...

    Well, the noise is there on internal calibration modes, where it connects the ADC input to VIO or GND.

    The stumper is that the noise is very low frequency, for the most part. There is nothing in the I/O pad that should cause such a long period And it's all amounting to only 1.6mV. I think it must be coming from the VIO supply or an external ground loop.
  • If its ground loop related, can you try outputting low on an adjacent pin to give a localized ground reference? (albeit through a 16 ohm N fet) ?
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