Can someone help me understand the mechanism by which the P2 straps to TAQOZ or EEPROM?
For those that have not been following on for the entire time of the development the onramp is a little steep. I've read what I believe are the most recent docs but obviously, not having followed every thought process during the design like some I'm missing a few key pieces.
I figured the best way to better understand would be to start at first principles. Can anyone help me rough-out how the P2 straps itself?
First, the stats:
- 512KBYTES of Hub memory.
- A single 32bit CNT register.
- 16 Semaphores.
- 8 Cogs. Each cog has: 4kbytes of RAM separated into:
- 512 longs register RAM (2kbytes)
- a second SEPARATE 512 longs of lookup RAM which can be futzed with by its neighboring core (2kbytes).
- No SPIN 'terp in ROM.
So - to my question:
When you power on the P2, is this an accurate representation of how it boots?
- 16k Boot ROM is loaded into (0xFC000-0xFFFFF) (except really 0x7C000-0x80000)
- Does cog0 then set its PC to 0xFC000 and start execution from Hub RAM in place?
- (ROM_Booter.spin2?) (written in straight PASM2) does things with fuses, resistors etc etc... to work out where it's going to boot from. If it's TACOZ that you wish, then it's already a part of the ROM image in hub and executed there on cog0 from hub ram?.
- Copies of the ROM appear to be embedded in the FPGA downloads - is it possible to get a copy of the ROM binary image to run through the emulator?
- Would that copy of the ROM just be a straight "Executable code from the first bit" or does it have checksums / preamble in front of it like the eeprom format? - I'm guessing the ROM image doesn't?