2-Cog, 128KB-Hub, 32-I/O P2

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  • YanomaniYanomani Posts: 701
    edited October 10 Vote Up0Vote Down
    TonyB_ wrote: »
    Could there be fewer boot pins in the smaller packages, namely two? This would leave 38 available, to match the IC pin count excluding power.

    It's up to you to decide how many pins would be dedicated for booting, in your particular application.

    The mention for up to eight (seven in fact, as they are currently defined) was made only logical-wise, to preserve the efforts already made done in develloping Rom-resident software contents.
  • TonyB_ wrote: »
    Something I've wanted for ages is a programmable drop-in replacement for a socketed 40-pin IC (CPU, VDP, ULA, etc.) which is why I like the idea of a P2 that could fit between pins 0.6" apart.
    If you get more creative on the PCB, the part does not have to fit between 0.6"
    You can use some SMD pins for example, so they do not go thru the board in the centre region.
    TonyB_ wrote: »
    Could there be fewer boot pins in the smaller packages, namely two?

    There was a single pin boot proposed for P2, that did not make the final ROM.
    Maybe that can be restored ?

    An issue with 2 vs 4 pins, is that means i2c vs SPI, and flash parts (strangely) come in SPI only.

    The EEPROM memory is more costly, so that results in
    512kb part is ~43c in a big package and 48c in a small one.
    1024kb part is ~85c in a big package and $1.40c in a small one.
    2Mb is $1.68 in a big package and $2.12c in a compact BGA

    In contrast, a latest package teensy 1.5 x 1.5mm SPI Flash series, costs 29c at 512k, 31c at 1Mb, and 40c at 8Mb

    There is discussion around including some Flash die stacked inside the package, which could use non-bonded pins.
  • Wuerfel_21Wuerfel_21 Posts: 189
    edited October 10 Vote Up0Vote Down
    Speaking of non-bonded pins, there may be a market for the regular 8-cog 512k P2, but in the same 40 pin DIP package as the P1, with half the pins non-bonded. I have no idea how much that would cost, but i assume not a lot.
    The DIP package is very nice for usage on breadbords or for people with terrible soldering (like me :P). It also has the advantage of being easily swappable when used in a socket.
    If they still make 64-pin DIP housings, i guess more pins can be had. Or maybe make it somewhat pin-compatible with the P1?
  • The 8 cog die will not fit in a DIP package, it's too big.
  • Scuse me Roy Eltham, but the current P2 die is only 8 mm x 8 mm, having, IIRC, a total of 124 pads in its pad ring, 24 of which are GND connections.

    If there is enough demand/traction, it can be assembled over a 64-pin carrier, four layer pcb, connected to it by gold wires and glob-toped with a proper sealing compound. Amkor can do this, for sure. It'll not be cheap, but doable anyway.

    There will be enough available area, left over the carrier pcb to mount a handfull of extra components too.

    Thermal dissipation will ever be a concern, so clocking options would be limited by that choice. A copper-core mcpcb could allow extra dissipation, but cost will ramp up, accordingly.

    But, sincerely, while inserting a 0.6", 64-pin dip, into a machined pin socket can be a matter of eyesight and pacience, removing it from the same socket could be only a matter of being lucky enough, to don't ruin it.

    Henrique
  • Would it be feasible and of any value to keep a few more or all of the B port I/O pads for internal connections to custom stacked dies as well as the flash?
    In science there is no authority. There is only experiment.
    Life is unpredictable. Eat dessert first.
  • Heater. wrote: »

    That is an interesting definition of "embedded" you have there.

    In my experience embedded systems have run from custom made computers using bit-slice technology built into 19 inch racks for controlling radars on battle ships, to the Intel 486 and Motorola 68020 used to be the Primary Flight Computers of the Boeing 777, to tiny MCUs encrypting data in police radios.

    Now a days embedded system processors include the full up Linux running machines you find in your domestic WiFi routers and the smarts behind Tesla auto-pilots and self-driving cars.

    I agree with Heater. "Embedded" should also apply to cyborg journalists embedded with out troops in Afghanistan.
    I am the Master, and technology my slave.
  • Yanomani wrote: »
    ...
    If there is enough demand/traction, it can be assembled over a 64-pin carrier, four layer pcb, connected to it by gold wires and glob-toped with a proper sealing compound. Amkor can do this, for sure. It'll not be cheap, but doable anyway.

    If you are going to multilayer, smallest size, rather than do a custom-bond glob hybrid, it makes more sense to look to do a BGA package version of P2.
    That gives you a solution that can be used in a lot more than just a DIP40 product.
  • Yanomani,
    I meant an actual dip chip package (like the P1's 40 pin DIP), not a PCB with pins (which I'm sure many people will make for the P2).

    kwinn,
    the pin pads take up a fair amount of die space with the P2 design, so I don't think that is feasible.
  • I understand it, Roy Eltham, and I was envisioning a 0.6" 64-pin solution, like the 68000.

    If it is a carrier board, or a ceramic package, like many products we had in the past, from, e.g., Analog Devices, its only a matter of budget.
  • I understant your point of view, jmg.

    Bga was ever among the options, and did found scarce aceptance by the ones then involved, by not being hand-soldering friendly.

    But now, when this wonderful popcorn smell is exciting each and every suricata suriccata (me included, a little fat and rusty, but still live, for sure), attracting our attention to P2, everything seems to be feasible. :lol:
  • Yanomani wrote: »
    ... I was envisioning a 0.6" 64-pin solution, like the 68000.

    Wasn't the 68000 0.9" ? If you are happy with 0.9", then the existing P2 package can likely fit there ?

    If you want smallest DIP, multi-layer, the existing P2 looks to fit in 0.75", which can give a 0.6" down-pin, where the inner most 8 are single-sided, and the rest can be thru-hole for alignment and strength. Does not need a costly special package, just multi-layer PCB, of tight design.


  • Hey, now I'm sure I must be very old! It didn't was 0.6", my bad (and not 0.9" too, jmg)! It was 0.8" or 20.4 mm.
  • Confusion here!

    Freescale (NXP) manual says it is 0.6" (Case 740-03 - L Suffix) as I did remember. Or NXP is wrong, or my memory didn't failed at all! Alleluia!
  • jmgjmg Posts: 12,618
    edited October 10 Vote Up0Vote Down
    Yanomani wrote: »
    Hey, now I'm sure I must be very old! It didn't was 0.6", my bad (and not 0.9" too, jmg)! It was 0.8" or 20.4 mm.

    Google finds a BOM for a 68000 Motherboard that lists

    Socket, IC Black, 0.9", Sn DIP-64 IC100 Mill-Max 110-44-964-41-001000 Digi-Key ED90061-ND
    Digikey says : 976 Can ship immediately

    Addit: Did you see this thread about DIP module variants, with a nifty soldering idea :
    https://forums.parallax.com/discussion/168755/propeller-p1-stacker-for-breadboards

    Looks like maybe that 0.9" socket could take the same nifty soldering trick, to make a P2 Stacker ?
  • Roy ElthamRoy Eltham Posts: 2,531
    edited October 10 Vote Up0Vote Down
    But how big of a die can fit in those 64pin dip packages like the 68000? It's not very big where the die goes, as I recall...

    Edit:
    The images here seem to indicate the die was pretty small inside the 68000's ceramic package: http://www.visual6502.org/images/pages/Motorola_68000.html
  • Yanomani wrote: »
    Page 177:
    https://nxp.com/docs/en/reference-manual/MC68000UM.pdf
    Two incarnations, perhaps? :o

    Nope, that says 0.9" pin to pin - I think you look at the package width, not the pin pitch ?

  • Please, jmg, look at dimension L (0.600 BSC)!
  • cgracey wrote: »
    I think the 2-cog version is more compelling than the 4-cog version. It's selling point would be the analog, smart pins, 2 processors, 128KB RAM, and CORDIC. It would be a squirrelly little thing.

    I've already got the schematics done for the 4-cog and 2-cog variants. They are just simple reductions of the 8-cog schematic. Turns out we get lots of pins, after all.

    I feel the same. And I think about it as a perfect interfacing IC for multiple purposes (I/O, display, ethernet phy, ...)

    Do you think it would be possible (or worth considering) to have two independent VDDIO suplies?
  • THERE ARE TWO of them!

    At page 177 (I was refering) and 178, 0.6" BSC.

    Yours at page 179 and 180, 0.90" BSC!

    Two Old Mariners, pulling the same Mermaid! :lol:
  • Ramon wrote: »
    cgracey wrote: »
    I think the 2-cog version is more compelling than the 4-cog version. It's selling point would be the analog, smart pins, 2 processors, 128KB RAM, and CORDIC. It would be a squirrelly little thing.

    I've already got the schematics done for the 4-cog and 2-cog variants. They are just simple reductions of the 8-cog schematic. Turns out we get lots of pins, after all.

    I feel the same. And I think about it as a perfect interfacing IC for multiple purposes (I/O, display, ethernet phy, ...)

    Do you think it would be possible (or worth considering) to have two independent VDDIO suplies?

    The pinout provides unique VIO pins for each set of four I/O pins. On the 2-cog 32-pin part, you could have 8 different VIO supplies.
  • Roy Eltham wrote: »
    But how big of a die can fit in those 64pin dip packages like the 68000? It's not very big where the die goes, as I recall...
    The idea is not to use a P2 die inside a 64p package, but instead to use those existing sockets for a PCB carrier, that is a 'scaled-up FLiP', on 0.9" centres. The standard P2 package can fit between 0.9" centres

  • Rayman wrote: »
    I think a low chip cost option makes a lot of sense.
    Might sell better than big one...

    So it might kill sales of the 8-cog chip?
  • Rayman wrote: »
    I think a low chip cost option makes a lot of sense.
    Might sell better than big one...

    So it might kill sales of the 8-cog chip?

    Maybe, or it might keep a sale with Parallax where the 8-core chip was considered and ruled out on power or board-space.

    For Parallax, better a 2-core P2 be selected than an AVR or PIC, right?
  • cgracey wrote: »
    The pinout provides unique VIO pins for each set of four I/O pins. On the 2-cog 32-pin part, you could have 8 different VIO supplies.

    Great! I think that both P2 versions (8 cogs and 2 cogs) will succeed in the current market segment between MCUs and low end FPGA.

    I don't think that a small footprint AND cheap 2 cogs version will hurt at all the 8 cogs version. They will complement each other AND can complement any other MCU/FPGA offering.

    If the NRE are substantially low, then it can be a good idea. But this depends of course in the grade of confidence you have with the current design. I think of it like some kind of financial hedging.

    If Ken have not been opposed to this idea is because he knows it could have commercial benefits. I think that two P2 versions is less risky than just one package option that tries to fit all needs. It's impossible for one MCU to fit all designs and that is the reason we have several hundreds of different MSP430, ARM Cortex, C8051, PSOC, XMOS, ... (whatever) MCUs.

    Also, with this 2 cog version Parallax can do a "try it out" ultra-cheap $10 or $15 board. Like those msp430 launchpad, Arduino micro/nano, PSOC prototyping kit, etc ...

    The biggest drawback you have by doing this now instead of waiting 1 year is that you don't know what you can safely trash from this 8 cogs P2 design to make the 2 cogs variant even smaller, cheaper, and faster.
  • Ken has already voiced that we can't expect the smaller part to be cheap just because it's smaller. The smaller part will have to other reasons for being selected. At least until the investment is paid for.

    Money is a placeholder for cooperation
  • For my uses, the smaller the better.
    A 5mm x 5mm package with 2 cogs would be great.
    I think Chip had said a 5mm x 5mm die, so I guess the package would be quite a bit larger than that.

    Something that would fit in a 14-pin dip between the pin would be ideal.

    Bean
  • 2 cog version makes sense for the education market.
    It will be the next arduino.
    There is no such thing as bad news.
  • I sure do like the idea of a $3, 2-core, 32- or 64-pin chip. More than 128kB of space would be nice... I'd take program space over almost anything else. More program space allows higher-level languages which allow faster development. C sure is cool - C++ is even cooler. C++ is cool, but real C++ (the STL) is a whole lot better. Real C++ is cool, but Micropython is even cooler. 512kB pretty much puts everything at our fingertips except full Linux (yea yea... Linux runs on AVR... let's stick to "usable" here). 256kB probably lets you run all the same programs, maybe with a slightly limited feature set. 128kB likely puts both Espruino and Micropython off the table. Espruino says "Espruino uses between 100kb and 200kb of Flash, plus roughly the same amount of flash as you have RAM if you want to save programs." And Micropython "128K ROM/8K RAM is the recommended minimum... "stmhal" and "unix" ports are around 280KB.... The reference MicroPython board, PyBoard, has 128KB of RAM."

    So... would I buy a Prop 2 with 128kB? Only if no other option was available. 256kB minimum is my preference.
    David
    PropWare: C++ HAL (Hardware Abstraction Layer) for PropGCC; Robust build system using CMake; Integrated Simple Library, libpropeller, and libPropelleruino (Arduino port); Instructions for Eclipse and JetBrain's CLion; Example projects; Doxygen documentation
    CI Server: http://david.zemon.name:8111/?guest=1
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