2-Cog, 128KB-Hub, 32-I/O P2

cgraceycgracey Posts: 10,478
edited October 10 in Propeller 2 Vote Up0Vote Down
Do you guys think there would be much of an early market for a reduced version of the P2 which has half of everything, in a similar 10x10mm exposed-pad 64-pin package?

For ON Semi to do this job for us, it is extremely simple, at this point. They have all the ingredients on-hand. I think the NRE on this would be quite cheap.

This chip would take half the power and cost about 1/3 less than the 8-cog P2. It would certainly run a little faster, too.
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  • potatoheadpotatohead Posts: 9,566
    edited October 9 Vote Up0Vote Down
    Is this in addition to, or at the cost of the target 8 cog chip?

    That said, if this is about getting two products, for say a bump on the respin price?

    And does the market need to be that early? Given it's run and validated, ideally in tandem with the target 8 COG chip, that mask set remains available. Run it on demand, and everyone makes their choices?

    Half the power, less cost and a bit faster? I think there just might be. That seems to drop right in between P1 and Beastie P2.

    We may find people, who are attracted to the 8 cog model, but just don't need as much, yet want to expand on what they are doing with P1.

    Could also be a great fit for education. Low power, pretty darn capable boards? That's likely a solid option in what Ken describes as an increasingly competitive market.

    In my mind, it comes down to available mask sets, and with this one, there will be three. This engineering one, the 8 Cog one, and the 4 COG one. Having those on tap, and in the catalog, along with P1, makes for a chip line. (minus the engineering one, which is just to get us going at this point)

    More to talk about, and a bit more granular best fit possible. It's likely a win at first glance, but I would really want to know how education shakes out. Could be meaningful, or it could be expensive, depending on what they will buy and why they will buy.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
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  • cgraceycgracey Posts: 10,478
    edited October 9 Vote Up0Vote Down
    It would be a new mask set, completely separate. This seems really easy to crank out. All the pieces are there and it's fresh on the people's minds at ON Semi.

    No new full custom layout is needed, just pulling out a bunch of I/O pad cells and reducing the die outline.
  • potatoheadpotatohead Posts: 9,566
    edited October 9 Vote Up0Vote Down
    Yeah Chip.

    It's really worth a look. Have a talk about education needs. That 4 COG chip might position near perfectly with them, and they can graduate to the bigger, better one at any time.

    Edit: I can tell you this!

    For me personally, assuming we've got 'em in the catalog, ready to go? I would get one or two P2 8 COG models, and a handful over some time, of the 4 COG models. Likely would setup on the 8 COG for development as that progresses, and deploy the 4 COGS where I can, because small, low power, potential speed.

    Use 8 COG chips where it's just demanding on a few axis.

    Professionally, and I may have an opportunity to place a P-chip into something in the near future, I would want to place the better one, lean and mean. Having that 4 COG model improves on that opportunity, from the little I know now.

    Others should comment on this. A chat about this, the future, plans may have value.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • I think there would certainly be a market

    At first glance having same number of GPIO as P1 might seem limiting, but you can point out things like 3 pin component video or 5 pin VGA (as well as what smartpins can handle)

    You'd want to be mighty sure about the NRE discount. But to be honest, the 8 cog version seems mightly floggable, and distraction factor that most worries me
  • potatoheadpotatohead Posts: 9,566
    edited October 9 Vote Up0Vote Down
    And having DAC / ADC on all those pins? Still more than many will need, meaning they've got room to work, expand, options. That's compelling.

    For some, if they get those auto displays, there is also really good one pin, color NTSC. (It's good for over 400 lines on a reasonable display, assuming reasonable color direction Just don't go RED / BLUE pixel by pixel, and it's going to perform better than people are used to, and it will do that because of the much better, cleaner output)

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • Solving of best clock gating should be resolved first, or in conjunction.

    If it's cheaper price then it'll sell, but will impact sales numbers of 8-cog model so pricing should probably have the same absolute markup until development is recoupled.

    Money is a placeholder for cooperation
  • I think having two products, basically a line of sorts, will prove compelling. One size fits all carries with it some perception of "fat" or waste. Now, that is not always true. Sometimes, it comes in handy too, but as a selection qualifier, one size fits all, loner wonder chip has to have impacted potential sales.

    Doing this would take some instances of that off the table, IMHO. Is that enough to fully check lost sales of 8 cog chips? Don't know, but I suspect the impact is less than we think it could be.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • evanhevanh Posts: 5,872
    edited October 9 Vote Up0Vote Down
    Chip,
    Halving the I/O and the resources should also halve the power pin count. That's then a 52-pin package, not 64. Dimensions too small? Well then, we have an incentive to find space saving don't we!
    Money is a placeholder for cooperation
  • For me, that just feels good. I want the speed of the P2 but I find myself drifting away from centralised control and more to distributed....And with IoT being all the rage....
    Failure is not an option...it's bundled with the software.
  • jmgjmg Posts: 12,616
    cgracey wrote: »
    Do you guys think there would be much of an early market for a reduced version of the P2 which has half of everything, in a similar 10x10mm exposed-pad 64-pin package?

    For ON Semi to do this job for us, it is extremely simple, at this point. They have all the ingredients on-hand. I think the NRE on this would be quite cheap.

    This chip would take half the power and cost about 1/3 less than the 8-cog P2. It would certainly run a little faster, too.

    Not so much of an 'early market', you would be far better to focus on getting P2 errata fixed first, then, think about variants.

    You could 'kite fly' with a proposed paper spec, as other vendors do, and they then decide to make something, when a large-enough customer 'comes out of the woodwork'.
    Meanwhile, anyone intending to use large volumes of a 64 pin P2, can develop using the 100 pin part.

    You may find, for example, that a BGA version of P2, can hit the small PCB footprint, which removes one reason to push for a separate die design.

  • jmgjmg Posts: 12,616
    evanh wrote: »
    Chip,
    Halving the I/O and the resources should also halve the power pin count. That's then a 52-pin package, not 64. Dimensions too small? Well then, we have an incentive to find space saving don't we!

    52 pins is non standard.
    Standard package choices would be 48 or 64 pins.
  • Any chance it could be fit into a 48 pin standard package with less separate power lines? Still not sure why we need separate IO power for every 8 IOs... Especially when they pretty much require 3.3v anyway, right?

    I think a cut down smaller cheaper version would be great, but also, get the first one done first.
  • jmgjmg Posts: 12,616
    Roy Eltham wrote: »
    Any chance it could be fit into a 48 pin standard package with less separate power lines? ...
    Using the TAB as GND, that's likely.
    32io + Xtals/rst/tst is 12 pins left for powers, which could be 6 core and 6io, or even 4 core / 4 io sounds ok.

    At that level, you could choose to offer 36io, giving users a clean 32io for their projects and 4 pins as Boot Loading.


  • cgraceycgracey Posts: 10,478
    edited October 9 Vote Up0Vote Down
    To fit into a 48-lead package, we would probably have to cut the hub memory down to 128KB. We might even need to get rid of the CORDIC. It becomes more about the die paddle size, than the number of pins.
  • Minor point: Like with FPGAs, keeping the same package for multiple chip variants is rather handy for board/system designers and can help defer the final choice of which device is needed for the application until after all the SW requirements have properly been determined, code developed and performance measured by using real hardware, not just in some simulation environment. Releasing multiple packages for the same part doesn't allow that luxury and would require additional board spins if changes are made.

    I still like the idea of enabling lower power applications, so a 4 COG version sounds interesting, though maybe that could be met by a lower specced clock gated 8 COG variant too.

    For example, one of my idle power concerns is with something like battery powered small robotics applications. A P2 is hopefully a great robotics chip with all it's IO and larger amount of RAM for more complex programs and cordic for analysis from various sensors etc. It's fine to need to chew plenty of power when everything is fully active and running flat out, but at times if lots of COGs are mostly idle waiting on timers before polling their sensors, or doing QDR decoding or controlling motors etc it would be nice to be able to conserve power and extend battery life/range/time of use of the robot. Simply scaling the overall P2 frequency down dynamically during idle periods may not be that easy to do if certain actions such as generating video or keeping some real time communications channel alive are still required during the idle time making the P2 need to run at higher or constant frequencies to function properly. Also some shared OBEX type COG objects are likely to be time sensitive and not always amenable to sudden frequency changes on the fly, which limits their use too.
  • I think 4 cog active signals (like we had on the FPGA) would be a nice feature.
    Melbourne, Australia
  • Ken GraceyKen Gracey Posts: 6,358
    edited October 9 Vote Up0Vote Down
    On this topic you'd normally expect me to squish the enthusiasm, but I'm open to the possibility. Once you've mobilized the equipment and the contractors are on site, it's cheaper to build the garage you didn't plan on. And, we've already got everything into this - might as well get it done while we have everybody's attention. An incremental increase could yield a substantial increase in revenue, even if the 4-cogger thieves a bit from the 8-cog version.

    We will meet with them tomorrow and talk numbers with ON. I've given Chip a bit of strategy in the discussion: first we'll finalize the change order for re-spinning P2; then we'll ask about additional costs for the 4-cogger. We won't cloud the critical path.

    As for education's needs, so much of what they're interested in has less to do with architecture and horsepower than one might think. The kinds of requests we receive include Python support, analog input, running Linux, having tutorials that align with their region's needs, etc. We could probably achieve everything with a 4-cog P2 (except the single-board computer Linux stuff).

    But there are concerns about this 4-cog concept: price expectations. From time to time I see mention of using ARM processors, cheap AVRs/PICs as competition to the Propeller. We won't be coming anywhere close to those price expectations, just to be clear. Four cogs isn't half the cost of eight cogs. The fixed NRE, packaging are somewhat similar but the die size is a bit less. We're a boutique player in this business and not in any position to dictate wafer costs in our volume.

    Ken Gracey
  • Actually, thinking about it some more, I say forget it for now. Get the current 8 cog version out where it can kick off all sorts of other efforts.

    If you do a 4 cog design because NRE is cheap right at this instant, fine, just don't tell us!.
  • Good strategy Ken.

    If Chip is right, you guys are in mind, project fresh, people familiar. There will be no better time. That's worth something to all parties.

    Hopefully On will deal some in the hopes of enhancing their share in all of this with a line, rather than a single chip.

    Fingers crossed!

    So long as it doesn't get tweaked all over the place, the revisions being done now, should apply to that one. Might just get lucky and end up with two working, production mask sets!

    Costs understood Ken. And some cost difference is likely the primary driver. IMHO, it's not hard to understand the difference is actually small.

    IMHO, this is more about product fit than anything else, and on that basis alone think it's a good line of discussion.
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • I definitely want an 8-Core P2 with fixed errata first.

    However, I also see a 4-Core P2 in my future.
    8-cores is a bit overkill for CNC and 3D Printers. I think a 2 or 4 core version would be awesome for those applications. A 4-core P2 could manage the print job, manage IO for a touch display and display controls on that same display from a single P2 controller. Many printers that have displays also have two controller boards. There's an opportunity to simplify such designs and lower printer costs with a single P2.

    I also think the world is looking for an Arduino replacement (8 or 32bit). P2 with Tachyon could be the ticket :-)

    Jason
  • Why are they looking for a replacement?

    Asking for a friend... :D
    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • Do you mean a 0.8 mm-spaced pin package, 0.65 or 0.5 ? (It doesn't fit in a DIP40 doesn't it ?).
  • Tubular wrote: »
    If you do a 4 cog design because NRE is cheap right at this instant, fine, just don't tell us!.

    I suggested to Chip "don't tell the forum members about your idea" to which he replied, "I already did - see the forum thread!".

    You guys are in charge of Parallax business, so be careful.

    Ken Gracey

  • The single-board linux computer stuff could eventually be done with a custom driver, something like a Pi (probably the Pi for broadest adoption potential), and the P2 on an add-on board, or a Zero added on to a P2 board.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • A small package low pin count version would be lovely for the majority of products but I can see it would make the P1 completely redundant except for DIP40 designs. On that note it also becomes easier to squeeze a P2 into a 40 pin DIP module and maybe Parallax could then do a FLIP2.

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  • Ken Gracey wrote: »
    Tubular wrote: »
    If you do a 4 cog design because NRE is cheap right at this instant, fine, just don't tell us!.

    You guys are in charge of Parallax business, so be careful.

    Ken Gracey

    Ken, in all seriousness, yes! I am confident many of us take that quite seriously. Somehow, we all got sucked into this adventure. It's a shared, common vision to do it a bit different, for reasons.

    Good ones, I believe, and have for many years now.

    I will be honest and say there are times I wish I could do more. Learning about all this stuff has been high value for me, but of higher value is seeing everyone come together and really work on what can make sense, augment that stuff Chip sees in his head.

    P1 is really * that * good. It's scale is just shy of what apparently is needed for broader adoption. This one P2, and potentially friend, has a much better scale / fit to possible use cases, and it's expanded on a few axis.

    Soon, maybe some of us * can * do more. At a minimum, some software is gonna help.

    In any case, it's bigger. Big enough to put a lot of new use cases on the table. Once people start doing stuff, I really do expect some of that to get outside this community, get a little attention.




    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • jmgjmg Posts: 12,616
    A small package low pin count version would be lovely for the majority of products but I can see it would make the P1 completely redundant except for DIP40 designs. On that note it also becomes easier to squeeze a P2 into a 40 pin DIP module and maybe Parallax could then do a FLIP2.

    There is quite a range of 64 pin packages at 8x8 or 9x9 for QFN, and 10x10 for TQFP, all of which would fit into a QFP44 courtyard.

    Or, a BGA packaged P2 might even allow that too ?
  • Could you get a die stack or dual die package that included a flash chip?

    I think having a single chip solution (no external flash) would be an awesome add to the 4 COG version.

    If you could just expose the flash pins on some of the external pins, then have the board layout loopback those pins, would be easy.

    I have to imagine that a 1MB serial flash would be very small.
  • They use their ONC5 process to build 2-layer interposer chips for this purpose. So, it could be done.
  • cgracey wrote: »
    They use their ONC5 process to build 2-layer interposer chips for this purpose. So, it could be done.

    Won't a stacked die raise new concerns about heat dissipation?
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