P2 Touchscreen + Memory

I'm looking for suggestions regarding a P2 touchscreen SBC. I've worked on several revisions of the "touchburger" trying to free up pins while keeping the memory access quick but have never found an actual excuse to make a pcb run. (I'm Average Joe btw ;) ) I still have a couple working touchburger boards but would really like an excuse to make a pcb run. Some thoughts for this design :

P2 Module : TBD

It sounds like the initial release of chips will be on a carrier board so knowing the details of the carrier board will dictate the support circuitry required. Assuming a P2D2 module or similar it should include everything needed.

Memory : 16Mb (1M x 16) Parallel 55ns 48-TSOP I @ $10.46

The original touchburger uses 2x AS6C4008 4MB 512kb X8 SRAMs. I was looking at moving to 1 x 16MB 1M X16 but this really isn't a lot of memory, about 2 full screen 800x640 images. I'm keeping the 16 bit data bus as it's handy with the displays. I've considered SDRAM but since I've never interfaced with drams i'm a bit iffy, maybe I could put a SRAM and SDRAM sharing the 16 bit data bus. I've looked at parallel FLASH as well, I know it seems pointless if you have a removable SD card but it would be nice to not need to load images from the sd. From the user interface perspective, loading a full screen 640 x 800 image from SD is painful.

?? SDRAM ?? FLASH ??

CPLD (for glue logic) : XC2C64A-7VQG100 @ $4.75

I've already tested this cpld for the previous version, worked great but the board space saving was a trade off with the extra 1.8v supply necessary. Since the p2 will need 1.8v core logic supply..

Touchscreen : Any SSD1963 or SSD 1289 or ?ili9341? touchscreen module.

There's some variations to the 40 pin "universal" connector. I'd like to have different modules without using the wire jumper method I've resorted to in the past.
https://www.ebay.com/itm/7-inch-TFT-LCD-module-Display-800x480-SSD1963-Touch-PWM-Arduino-AVR-STM32-ARM-/311523810931


Form Factor : TBD

I was considering using the same form factor as the 7" touchscreen but in early layout tests this left a large empty board area.


Comments

  • 18 Comments sorted by Date Added Votes
  • jmgjmg Posts: 12,446
    edited September 30 Vote Up0Vote Down
    I've seen some SPI displays for RaspPi on eBay, that claim 125MHz SPI, so connecting one of those to a P2 streamer could be interesting ?

    Addit : oops, no, that's 128MHz on the banners
    Search eBay for 128M SPI 60Hz For Raspberry Pi for smaller 3.5" screens.
  • Spi displays become very interesting with the streamer, although those displays seem to interface to 5v? I've been watching the HDMI thread because I've looked at the hdmi displays a few times. Might have to get a few different displays to play with although I really like the 16b parallel displays. 21 pins really doesn't feel like a lot, I'm working on a design for the p1 that will leave 6 or 7 free pins, hopefully that gets more interest than the no pins board did :wink:


    The real performance bottleneck that I've experienced is SD storage. While they're handy, loading anything larger than a 320 x 240 image is excruciating. Overclocking the p1 to 96mhz helped but I think the solution would be a large parallel flash chip. Maybe 2G or 4G.


    I keep coming back to something like

    FLASH - NAND Memory IC 2Gb (128M x 16) Parallel 48-TSOP @ $7.70
    FLASH - NAND Memory IC 8Gb (512M x 16) Parallel 48-TSOP I @ $13.31

    I've had the idea that a binary executable and a "GUI pack" could be stored on flash for much faster access. The whole wear leveling and file table turned me off of the idea some years ago but I don't really see a way around it. Even 4 bit sd card access is going to be slow.

    I'm still trying to figure out a board that can be used with the P2 AND P1. The P1 design I've been studying as a starting point had a QFP44 but maybe I should switch it to a DIP 40 and and copy the 10pin connectors parallax is showing for the render of their development board? Then there's the power problem, given the 7" display takes 620ma @5V for backlight :angry: That's probably asking more than the development board will have.

    I guess I'll keep toying around with my designs for the p1. Getting close to releasing some details in the p1 forum!


  • cheezus wrote: »
    ...Then there's the power problem, given the 7" display takes 620ma @5V for backlight :angry: That's probably asking more than the development board will have.

    P2 boards do not generate 5V supplies. They can take 5V as a power source, and 2A seems common for 5V USB chargers.
    Raspberry PI 3 has created some market for 5V / 3A supplies.

    Depending on the switchers they finally use, P2 boards might be able to tolerate higher voltages, for Vin, opening up NiCAD battery packs for example.

  • Thanks jmg! I wasn't 100% on the dev board at the time. I think I've got it now, only needing a small 1v8 supply for the cpld. I've got a board about ready to send to fab, i'm still trying to figure out what to do with the 4 free pins on the cpld (probably bring out to another header) and P22 and P23 (again probably another header) I am considering sending p22 and p23 to P1 style audio out rc network and heaphone jack. Here's a render of just the signal layers (top and bottom). I decided to do a 4 layer board for this design, considering a run of 10 boards although if anyone is interested I might get 20.


    I'm probably going to pick one of those SPI displays up in the next couple weeks just to play with. It will be interesting to see the difference between the 3.2" I already have and the 3.5" I've got a P1and supply board I've been working on, when I get that design closer I'll post in the P1 forum. Any thoughts are greatly appreciated!
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  • jmgjmg Posts: 12,446
    edited November 18 Vote Up0Vote Down
    cheezus wrote: »
    Thanks jmg! I wasn't 100% on the dev board at the time. I think I've got it now, only needing a small 1v8 supply for the cpld. I've got a board about ready to send to fab, i'm still trying to figure out what to do with the 4 free pins on the cpld (probably bring out to another header) and P22 and P23 (again probably another header) I am considering sending p22 and p23 to P1 style audio out rc network and heaphone jack. Here's a render of just the signal layers (top and bottom). I decided to do a 4 layer board for this design, considering a run of 10 boards although if anyone is interested I might get 20.


    I'm probably going to pick one of those SPI displays up in the next couple weeks just to play with. It will be interesting to see the difference between the 3.2" I already have and the 3.5" I've got a P1and supply board I've been working on, when I get that design closer I'll post in the P1 forum. Any thoughts are greatly appreciated!

    Nice board, if you are doing a 100 pin logic device, and fast LCD, you might consider a footprint that has some RAM to allow LUT in Logic ?

    Maybe LCMXO2-640HC, or LCMXO2-1200HC or LCMXO2-2000HC ?

    I like the look of ICE40UP5K-SG48I, but that's 48 pins so may not match your params (but it does have 1MBit RAM) & Lattice have finally released an Eval Board for the 48 pin version ICE40UP5K-B-EVN


    This could also be used to test P2 with PLD pathways faster than 128MHz SPI. ( it also gives more bits per cycle on P1)
    eg Dual-SPI can double the bit rate, and DDR-double-SPI would halve the P2 SysCLK

    Quad SPI is faster still, but needs more pins.

    You may have room on that PCB for an 8-pin PSRAM ? - https://lcsc.com/product-detail/RAM_Lyontek-Inc-LY68L6400SLIT_C261881.html
  • cheezuscheezus Posts: 13
    edited November 18 Vote Up0Vote Down
    The schematics are kinda messy because I started with the free version of eagle and then when I started laying out the board I quickly realized this was a perfect candidate for a 4 layer board I paid for a month of the standard. I'll probably be getting a year license once this one expires.

    I'll attach the 4 sheets but as it stands I have 4 unused pins on the cpld (coolrunnerII), and also an unused SPI chip select from cpld. I will probably be breaking out the SPI chip select from the unpopulated FLASH footprints on the 40 pin display carrier boards, along with the SPI MOSI, MISO and CLK. Trying to decide if I should include 3v3 and ground on breakouts. I'm not really happy with all the 0.1" headers all over the place. The 2x 2x3 pin connectors to the right of the cpld are JTAG and 3v3 GND and 1v8. I have the jtag supply routed to 1v8 but am thinking of routing directly to JTAG connector and (or) 3 pin voltage select header. There's also the option of just using testpads on the bottom layer for JTAG and build a pogo pin programmer... I need to consider this more.

    I had considered adding a 16 bit SDRAM or at least putting a footprint on the board but that would mean moving up to a xc2c128 for the 100 pins as opposed to the xc2c64a's 64 max pins. They have a common footprint so I'm still considering adding it on rev2. I was considering adding a 3.5mm jack and RC network for headphones but I really don't like the way the through hole jack fit.

    I'd have to think about how to handle the QPI pins. I had the idea to use 4 parallel QPI flash chips to drive a 16 bit bus but was never able to really make that work. In the current design I have the SPI bus on pins p12-p15 and I believe I used pins p16 and p17 for the 1 of 4 select. SD card is SPI device 4 since all pins will have pullups enabled on the cpld so it will default to SD. (I hope, I've tested the CoolrunnerII pullups on a breadboard design so seeing this all work on a pcb after 6 years will be amazing)

    I'll open the CPLD design tool and get a capture of that ratsnest once I boot my other PC. Need to see how I could fit a QPI on the bus. Perhaps it may be best to use pins below the SPI bus for the SPI select or move the select pins to p19 and p18 to free up p16 and p17. Once again, need to think about this.

    The idea of using DDR is interesting because the the CoolrunnerII devices have Optional DualEDGE triggered registers and Clock divider (÷ 2,4,6,8,10,12,14,16) but the clock divider is only available on the 128 and larger devices. Perhaps it would be wise to allow the 64, 128 or 256, there's a couple more power pins and associated decoupling, as well as breaking out the additional pins.

    I had the idea of using the propeller to program the CPLD, allowing on the fly reconfiguration from SD card. There's lots of possibilities here, I need to look at the current CPLD schematic (I wish I could wrap my head around Verilog) as I can't remember what the Fmax on the compile is. The Fmax on the CoolrunnerII datasheet is 263mhz for the 64A, 244mhz for the 128 and 256mhz for the 256, all available in the VQ100 package.

    The overview for the CoolrunnerII family is here, I'm not 100% on the clock divider part. Maybe a REV3 can use the larger CPLD and SDRAM.
    https://www.xilinx.com/support/documentation/data_sheets/ds090.pdf

    *edit
    I just started thinking about LUT in hardware and this gives a compelling version to step up to a 128 or 256. The 64a has quite a bit of logic left and I was trying to figure out what to do with it. I'll have some numbers in a few!
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  • cheezus wrote: »
    .... I had the idea to use 4 parallel QPI flash chips to drive a 16 bit bus but was never able to really make that work.
    It should work, but could be easier if the PLD split the address 4 ways for the command/address preambles

    Checking into SPI larger FLASH I see
    1Gb $3.58
    2Gb $5.24
    4Gb $6.75
    and NOR flash comes up to 512Mb
    cheezus wrote: »
    I just started thinking about LUT in hardware and this gives a compelling version to step up to a 128 or 256. The 64a has quite a bit of logic left and I was trying to figure out what to do with it. I'll have some numbers in a few!
    A reasonable size LUT would need RAM.
  • cheezus wrote: »
    The schematics are kinda messy because I started with the free version of eagle and then when I started laying out the board I quickly realized this was a perfect candidate for a 4 layer board I paid for a month of the standard. I'll probably be getting a year license once this one expires.

    Instead of spending more money on Eagle, why don't you just use KiCAD? It's free and open source and can do many-layer boards. I've designed multiple two-layer boards in it, and it works great. There are Eagle -> KiCAD conversion tools, though I've never used them and I don't know how well they work.
  • cheezuscheezus Posts: 13
    edited November 18 Vote Up0Vote Down
    jmg wrote: »
    cheezus wrote: »
    .... I had the idea to use 4 parallel QPI flash chips to drive a 16 bit bus but was never able to really make that work.
    It should work, but could be easier if the PLD split the address 4 ways for the command/address preambles

    Checking into SPI larger FLASH I see
    1Gb $3.58
    2Gb $5.24
    4Gb $6.75
    and NOR flash comes up to 512Mb

    I was able to get the P1 working with a QPI flash and get it into QPI mode, but replicating the command and address across the 4 chips drove me to rage quit. I'm sure it could be done and I might revisit that at some point. I'd like to wrap my head around the parallel FLASH chip before I start trying to get tricky with hardware. This design is intended to be optimized for low latency memory access and even with a QPI chip there's quite a few clocks of setup.
    cheezus wrote: »
    I just started thinking about LUT in hardware and this gives a compelling version to step up to a 128 or 256. The 64a has quite a bit of logic left and I was trying to figure out what to do with it. I'll have some numbers in a few!
    A reasonable size LUT would need RAM.[/quote]

    This is true, I guess I was thinking about a small group of registers as LUT but it would be very limited. I was trying to post the current CPLD schematic but my desktop suddenly doesn't like my LAN? There's really not much to it. I'm showing a Fmax of 140.845mhz for p21(group change clock) 227.273mhz for p20 (address counter clock). Switching the up/down counter for an up only would improve the fmax on P20 but seems pointless considering the AS6C1616 SRAM 70ns or 55ns read/write cycle time. That puts fmax on 55ns SRAM at just over 18mhz if I understand that correctly. Not sure about FLASH and that's second priority right now. The displays I've used max out at 20mhz. None of this has been any concern since I the p1 was topping out at 12.5mhz anyway.


    I'm going to go ahead and drop that PSRAM chip on the board. I'm not exactly sure what you had in mind with the Lattice part, if you were talking replacing the current CPLD or adding it alongside? I'm not familiar with the toolchain so there's that learning curve. :worried:
    cheezus wrote: »
    The schematics are kinda messy because I started with the free version of eagle and then when I started laying out the board I quickly realized this was a perfect candidate for a 4 layer board I paid for a month of the standard. I'll probably be getting a year license once this one expires.

    Instead of spending more money on Eagle, why don't you just use KiCAD? It's free and open source and can do many-layer boards. I've designed multiple two-layer boards in it, and it works great. There are Eagle -> KiCAD conversion tools, though I've never used them and I don't know how well they work.

    I've heard of KiCAD but been using eagle forever. I'm always weary of new toolchains and the associated learning curve.
  • Instead of spending more money on Eagle, why don't you just use KiCAD? It's free and open source and can do many-layer boards. I've designed multiple two-layer boards in it, and it works great. There are Eagle -> KiCAD conversion tools, though I've never used them and I don't know how well they work.
    KiCad has direct eagle import, which works quite well.

    cheezus wrote: »
    I've heard of KiCAD but been using eagle forever. I'm always weary of new toolchains and the associated learning curve.

    Download it, and load your current Eagle design into it, so you have something familiar to work on.
  • cheezus wrote: »
    ..I'm not exactly sure what you had in mind with the Lattice part, if you were talking replacing the current CPLD or adding it alongside? I'm not familiar with the toolchain so there's that learning curve. :worried:
    The idea was to simply swap into the same footprint, shuffling power/ground as needed.

  • CERN has been putting a lot of funding into developing KiCAD. It's getting better with every version and the time between major versions has greatly decreased. They juts did 5.0 and they have a solid roadmap to get to 6.0.

    With the closed source tools, you never know when the vendor is going to pull the rug out from under you - especially hobbyist use. One day they might offer a $100-one-time hobby version with reduced PCB size, the next day the entire company gets bought up and it's 'software as a service' and you can't even use the software without an Internet connection and it's a $75 per month subscription fee.
  • Went to download KiCad last night and was greeted with:

    Please note that a last minute bug was found in the Eagle schematic import feature too late to be fixed in this release which is expected to be fixed in release 5.0.2. If you need to convert Eagle schematics you may want to hold off upgrading until 5.0.2


    OFFFFFFFFF COURSEEEEE!


    I added the PSRAM footprint, P0-P3 data, P4 CLK and /CS from CPLD. Getting close, need to add some more headers. I'll try KiCad when I start on revB and will probably look into the lattice part for that version as well. As you can see there's still quite a bit of room on the board. Still looking for ideas on how to fill it up.
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  • cheezus wrote: »
    .. Still looking for ideas on how to fill it up.

    If you are feeling ambitious, search eBay for 4" inch or 3.97" inch TFT LCD Display Module 480x800 with Resistive Touch Screen
    I've seen a Raspberry Pi module form of this, claimed 60fps, which I make ~ 23MHz strobe rate
    That is FFC, but includes the connector. and you already have many 0.5mm footprints, and it has a lot of pixels for that size screen.

    Is your plan to have the CPLD+SRAM stream to the LCD continually ?
  • One of the ideas I've had is to get the raw pixel clocked displays and build something like this ;

    https://www.sparkfun.com/products/12725

    Using the raw displays like this ;

    https://www.adafruit.com/product/1774
    or
    https://www.adafruit.com/product/1596


    While it's possible there's no benefit as far as I can tell, other than form factor and it adds a lot of complications. I like being able to develop on either the 3.2" 320x240 or 7" 480 x800 by just swapping display modules (and software of course).


    This is a continuation of the design here :
    https://forums.parallax.com/discussion/comment/1107747/#Comment_1107747

    The idea is to load tiles or GUI elements to SRAM (or flash) so when a program needs them, they can be displayed quite quickly. I was hoping to use the memory for LMM to allow me to build a midi tracker. That's still way over my head at the moment. I've been drooling over this lately ;

    http://www.akaipro.com/products/mpc-series/mpc-touch

    or something like this ;

    https://www.soundonsound.com/reviews/roland-mv8800

    but for midi only. Okay so probably closer to something like this;

    http://www.muzines.co.uk/articles/roland-mv30-studio-m/790


    I had an MV-30 and loved how intuitive the sequencer was to use. It's internal sounds were exactly what you'd expect from Roland. A p1 based version would have a more "retro" sound set but it seems like the P2 would be the sweet spot for a sampling synth.
  • ElectrodudeElectrodude Posts: 1,197
    edited November 18 Vote Up0Vote Down
    cheezus wrote: »
    Went to download KiCad last night and was greeted with:

    Please note that a last minute bug was found in the Eagle schematic import feature too late to be fixed in this release which is expected to be fixed in release 5.0.2. If you need to convert Eagle schematics you may want to hold off upgrading until 5.0.2


    OFFFFFFFFF COURSEEEEE!

    I just tried importing an Eagle schematic in my KiCAD 5.0.0, and it seems to have worked fine. The bug might only turn up in certain cases. Why don't you try it anway and see what happens? If it doesn't work on the current 5.0.1, try the previous 5.0.0, which I have and which works. Chances are it will work, and if something goes wrong, your schematic looks simple enough that you should be able to fix any by hand.

    EDIT: The board I imported as a test was Adafruit's Powerboost 500C. I ran the schematic ERC and the PCB DRC from KiCAD. The ERC complained that labels were done the Eagle way and not the KiCAD way, but this isn't really a problem (though it's a bit messy in KiCAD) and is easy to fix or ignore. The schematic import looked wonky until I told it to regenerate copper pours. The DRC gave two pad-near-pad errors that I didn't investigate.
  • cheezus wrote: »
    I added the PSRAM footprint, P0-P3 data, P4 CLK and /CS from CPLD. ... Still looking for ideas on how to fill it up.

    I notice these are about to arrive at Mouser - larger and faster SPI memory.
    IS62WVS5128GBLL 4Mb QSPI SRAM x1, x2, x4 2.7~3.6V 45MHz -40 to 125°C 8-SOIC Prod Serial SRAM

    Same footprint as the PSRAM, but without the refresh, so can be useful for testing.
    4x of those could drive the LCD directly with a clock-gap scheme used to update the RAM, when the LCD is not clocked (so it ignores the WR bus info).

    4x is also just enough to hold a 16bpp image, out to 480x800 display.

    Such a 4 x Quad design just might be able to dispense with the CPLD ?
  • cheezuscheezus Posts: 13
    edited November 19 Vote Up0Vote Down
    I'll download kicad once this board is "done"... or at least rev1 is off to fab. It's getting close, still not sure about all the headers that have popped up all over the place. There's definitely room for improvement on this design and I need to make sure the QPI footprint won't interfere with group changes. I may need to move things around a bit. I also don't know about the silk screen. I think the labels might be a bit small. Thinking about putting pin labels on the back of the board as well.


    *edit

    I believe a 4xQPI could replace the CPLD. For most applications it would probably be fine. Since I want to use the memories for more than just display buffer, all those extra clocks for command / address setup seem like a bad thing. Plus with the CPLD I'm able to overlay the touch spi and SD pins over the 16 bit data bus. I'll try to get a couple images of the glue logic tonight so you can see what I've got.

    *aedit
    attached cpld schematic. note, spi/qpi enable is not assigned yet. I need to come up with a list of the functions of the 21 muxed propeller pins. I there's some pins free in group 3 and group 0. Group 4 is unused so 21 free pins.
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