PCB Design criteria for new chip.

T ChapT Chap Posts: 3,902
edited August 6 in Propeller 2 Vote Up0Vote Down
I’m wanting to start collecting the known basics for the design. There is some info it Peter’s threads but there’s a lot in there. Some of which is not completely settled?

1. Power supply but up sequence? 1.8v core first then 3.3 analog second? If so what delay. What options to sequence the power? Cheap micro. Or the 1.8 powers up then enables the 3.3? What happens if 3.3 goes first by some accident.

2. 1.8v reg current rating and preferred type. LDO or switching.

3. 3.3v reg current rating and type LDO or Switching

Since a lot of boards need 5 already for various uses, I use a hefty 2a 5V switching so that a large input voltage range can be used and there is power for a lot of of peripheral boards to connect. This means a short drop to 3.3 and to 1.8. But if 1.8 should in theory go on first there needs to be some enable for the 3.3v.

Here is what I use for a main 5V supply for a system that needs 5V at many places:

http://www.analog.com/media/en/technical-documentation/data-sheets/10765fc.pdf

Obviously this is overkill for most boards but the idea is the same. Large input range, switching so no heat getting down to 5. Then low heat to get to lesser voltages.

Heat sink. Chip says 4 SQ in copper. Or less if the chip isn’t being ran maxed out. Possible the bottom layer or add on heat sink or pcb designed for heat.

5V tolerant inputs like P1? I have abused many hundreds of P1’s with low value input resisters even 1k and never had a problem. Is the new device going to take Similar abuse.

Boot up. So the eeprom is out on this device. SPI flash is the simplest boot device, behaving just like the eeprom did ie some fixed area for bootuo then you can use the higher unused space. Or use the SD card if you prefer that functionality.

This is the first batch I have in mind.











Comments

  • 4 Comments sorted by Date Added Votes
  • You can get a dual voltage 3.3v/1.8v regulator that has the power sequencing built in. Much simpler.
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • jmgjmg Posts: 12,616
    edited August 7 Vote Up0Vote Down
    T Chap wrote: »
    1. Power supply but up sequence? 1.8v core first then 3.3 analog second? If so what delay. What options to sequence the power? Cheap micro. Or the 1.8 powers up then enables the 3.3? What happens if 3.3 goes first by some accident.
    I don't think that any 'damage' path has been mentioned, but the reset pin also comes into this mix.
    Unclear is where Reset applies to the 1v8 and 3v3 domains, and if it async to the pins (does not need a clock - many small MCU have async resets to the pins)
    If you want 'no surprises' startups on the pins, and power downs too, then the core should be working before the reset is released.
    The internal Reset timer gives a little skew tolerance, but it will likely need a real chip to shake out any ordering issues.
    eg I would avoid too soft a soft-start on the 1v8 core, and I've listed before SMPS parts with a PowerGood pin, that can assist reset.

    Something like
    AOZ3024PI looks useful wide Vcc, (4.5~18V), 3A, and PGood out, ~31c/3k
    or
    NCP3170A/B OnSemi 4.5~18V 3A PGood 38c/2.5k 33c/2.5k Mouser. (if a part fits ok, there is some appeal to selecting OnSemi :) )
    or
    RT2751 4.0~17V 1.5A PGood 51c/2.5k
    or for lower Vin ranges,
    P3402KTTR-G1 2.7V~5.5V TSOT26 synchronous rectifier PGood 2A 12c/3k

    T Chap wrote: »
    2. 1.8v reg current rating and preferred type. LDO or switching.
    That's a simplicity/power trade off - for initial boards a SMPS as an option at least seems a good idea, until typical powers are defined.
    If you want best analog performance, SMPS may need to be 'kept clear', and even a SMPS pre regulator then LDO final stage could be needed.
    Analog tests should be done with a quiet LDO and then checked again with SMPS active, to check for the impacts.
    T Chap wrote: »
    3. 3.3v reg current rating and type LDO or Switching
    As above, but this more relates to 3v3 loading external to the P2 - ie more a system question than a P2 question.


    T Chap wrote: »
    Heat sink. Chip says 4 SQ in copper. Or less if the chip isn’t being ran maxed out. Possible the bottom layer or add on heat sink or pcb designed for heat.
    The more cooling the better... There is also 1oz vs 2oz and 4L vs 2L and even a fan...
    T Chap wrote: »
    5V tolerant inputs like P1? I have abused many hundreds of P1’s with low value input resisters even 1k and never had a problem. Is the new device going to take Similar abuse.
    Hehe, that's not so much '5V tolerant', as injection current tolerant. As with P1, you need to be sure the 'other' 3v3 loading prevents drifting up from those injection currents, and over-voltaging the part.
    During reset, those currents might be quite low.
    Note also that injection currents into CMOS parts usually activate lateral parasitic transistors, so beware effects on adjacent Analog pins...


  • What idea were you thinking regarding the power good output pin. You mean ie a micro to watch the pin and only allow reset after power is solid? I don’t follow why you care about reset timing on 1.8v power up. You would only use reset to program and power wokldnalready be on. It sounds like you are saying to use SMPS to get from a higher ie 12v down to 5V the LDO for both 1.8 and 3.3 for best overall noise levels.
  • jmgjmg Posts: 12,616
    T Chap wrote: »
    What idea were you thinking regarding the power good output pin. You mean ie a micro to watch the pin and only allow reset after power is solid? I don’t follow why you care about reset timing on 1.8v power up. You would only use reset to program and power wokldnalready be on.

    Power Good is an Open Collector output pin from the regulator itself, that stays low until the Vcc is in range, and also goes low at power off, as the power supply falls slowly.
    Reset timing matters because you do not want the core to be running outside spec. - eg a too-slow rise, or a brownout, could drop core to 1.3V, where things 'almost' work,
    You can 'or' tie reset sources, so UART reset for download can still work, and if you have 2 SMPS, you could combine those PGood signals.

    One of my favourite 'killer tests' is to feed a slow triangle wave into a Vref pin, and vary the Vcc valley depth.
    T Chap wrote: »
    It sounds like you are saying to use SMPS to get from a higher ie 12v down to 5V the LDO for both 1.8 and 3.3 for best overall noise levels.

    Certainly, big drops like 12V to 5V would usually be a SMPS, and the 1.8V could be SMPS alone, from 5V (as that's cheaper) or it could be SMPS + LDO.
    The 1.8V is likely to be more noise tolerant than the 3v3, as the Analog stuff is 3v3, but you would still need care to avoid the 1.8V GND noise. ( In another thread Chip mentions which 3v3 pin powers the PLL/Xtal)

    If you do use a 5V to 1.8V SMPS, that does reduce the 12V loading as the 5V drain is less with a SMPS than a LDO.
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