P2D2 - An open hardware reference design for the P2 CPU



  • Updated artwork with RTC option as standard placed on main component side. I still have to reorder the RPi header but that is straightforward.

    1983 x 1256 - 2M
  • Personally I don't have plans for this clock generator, but others might and perhaps the phase adjustment of the main clock could help with tweaking sysclock/1 operation of HyperRAM.
  • In case you didn't see this update to my earlier post on HyperRAM Peter.

    Update: phoned ozpropdev and he said the control pins are fine. It's arbitrary in his driver code. Having the clock signal immediately following the 8 bits of data may help with any byte banging using 9 bit direct writes to portB with alternating top bits for the clock. You could set CS low manually before the transfer and directly send bytes+clock using individual writes, so I think the mapping above is handy.
  • Here is the latest artwork pending design rule checks and tweaking. The RPi header has P0..P26,P28,P30 while only solder bridging a single ground pin for P18. All the signals are available in order on the main headers as well as the SMD headers.
    1571 x 1241 - 495K
    1565 x 1240 - 365K
  • Cool. Glad you were able to get most of the contiguous pin group to squeeze through Peter, this can help if people want to make 24 bit parallel RGB LCD breakouts using these pins (though that's only one use). Be nice if P27 could replace P30 but that gap in the upper byte is less of an issue than the original missing P18 was as these upper pins can always be LCD control pins and are a little more flexible, though P24 is rather useful to keep for sync/DE reasons with the DAC and you've still got that one too.
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