P2D2 - An open hardware reference design for the P2 CPU

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  • jmgjmg Posts: 13,782
    jmg - as I "finish" something functional I'm always tempted to push something else in. But where do we stop? Isn't a crystal option or the Si3531A with either a crystal or TXCO more than just an option? Besides, the new silicon's PLL should be a lot better.

    The Pin1 suggestion was to allow users to choose where to 'worm' pin 1 to, as some OSC footprints have very little solder-edges.
    The Via suggestion allows the (VC)TCXO to more easily drive into P2, (using a short wire) so a Si5351 is more optional.
    If the new silicon PLL's really do operate better, the Si5351 is less likely to be needed.
    Chip made only minor changes to VCOs so I'm not sure 'a lot better' is expected ? Low PFDs will still be a problem.
  • @jmg - point taken but I'm always after a "cut-off" as one of the options :)

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  • I suppose I could allow for a 1206 polyfuse since they are a lot cheaper than their smaller cousins.

    Well if you ultimately do decide to fit such a 1206 footprint in that vicinity, the option of being able to strap it to either VIO or 5V would be handy too in case you ever wanted to power an external cheap ESP8266 (eg. ESP-01S type) WiFi module plugged into your top edge pins for doing remote downloads to your board without needing another external regulator for it or strapping it up to the other 3.3V rails/pins from your LDO regulator. I vaguely recall I discussed this idea earlier with your first board rev. Might add some more flexibility with a simple SMD footprint position option, assuming it fits in that PCB space and these WiFi modules are okay with 3.6V.
  • I've used polyfuses before and while I have added a footprint for one I now feel that it is just as easy to use a current limit switch instead such as the TPS2051 etc since they are also quite cheap. but far more precise.

    The ESP8266 is specified to operate up to 3.6V so I don't see the problem in that it can run straight off VIO and the voltage difference with I/O only starts to become a problem when it is greater than 300mV.

    Maybe I should make an sandwich module that includes HyperRAM and an ESP8266? (This thin pcb module surface mounts to the back of the P2D2).



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  • TubularTubular Posts: 3,646
    edited 2019-04-23 - 07:17:59
    One other advantage of running at 3v6 is that WS2812 "neopixels" go above their 70% of 5v threshold (3.5v) and work a lot more reliably.

    edit: or is the P2 still running post LDO at 3v3?
  • The 3.6V is mainly for feeding the dual 3.3V LDO, one each for port A & B. Port A power is available near P0 and Port B switched power is available near P63 but the pins near P31, P32 are 3.6V straight from the switcher and have at least 1A or 2A rating.

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  • roglohrogloh Posts: 1,146
    edited 2019-04-23 - 22:40:51
    The 3.6V is mainly for feeding the dual 3.3V LDO, one each for port A & B. Port A power is available near P0 and Port B switched power is available near P63 but the pins near P31, P32 are 3.6V straight from the switcher and have at least 1A or 2A rating.

    Yeah that was what I was thinking. A WiFi module can potentially draw bursts of 300mA or more and I was thinking it would be good to draw it from VIO to not burden the other 3.3V LDO which in some cases your might want to keep quiet for the PLL, audio supply etc, or already be loading up with your normal application I/O loads.

    A 1206 polyfuse footprint connected on one side from the external positive + power pin net at the top of your board into either 5V for standard USB/external powering situations, or alternatively to VIO (via some solder jumper strapping or dual footprint position) could allow current to flow in either direction for these cases and could then support a WiFi module to easily connect directly to the P2D2 board, no regulators required. We could then consider it as a system supporting a self contained "wireless prop plug" for remote debug/downloading purposes etc. Very handy.
  • Peter JakackiPeter Jakacki Posts: 8,512
    edited 2019-04-25 - 13:51:08
    Looking at this artwork I'm wondering now if I should bother with a great big hole under the P2? I mean, despite Chip saying it would be a good idea it didn't end up on the eval board anyway. I ended up using cheap TPS22919 protected load switches for the SD power and for +5V/USB protection.
    btw, Four P2D2 pcbs fit within the P2-eval pcb size with room in the center.
    P2D2r2-1.png
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  • That great big hole helps with hand-soldering. The EVAL's being pick/oven built did not require the hole.

    Do you expect anyone to hand-solder P2D2?
  • Peter JakackiPeter Jakacki Posts: 8,512
    edited 2019-04-25 - 14:06:44
    VonSzarvas wrote: »
    That great big hole helps with hand-soldering. The EVAL's being pick/oven built did not require the hole.

    Do you expect anyone to hand-solder P2D2?

    To me, hand soldering makes absolutely no sense when solder paste is readily available and all I use is a cheap toaster oven (and technique).
    It is just so easy and anyone attempting assembling a P2D2 should not hold back from doing it this way. You have no idea how I cringed when I saw Chip lining up the P2 on the board under the big magnifier and using an iron!!!

    But I wonder how much less efficient the heat transfer might be leaving the hole there.

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  • btw, Four P2D2 pcbs fit within the P2-eval pcb size with room in the center.

    It makes me wonder...

    If P2D2 layout could be easily expanded, at the longer sides, with paired connector footprints, crafted to exactly match P2-Eval...

    If, at the same time, the P2D2 underneath-resident HyperRam add-on could be logically and phisically shared thru the now interconnected buses...

    Some spare flag bits would last, every 16 contiguous pins; enough for an interlocked, handshake-driven parallel protocol.

    A up-to five, P2-based cluster? With multimega bytes of shared Ram memory?

    It makes me wonder... :lol:

    Henrique
  • jmgjmg Posts: 13,782
    To me, hand soldering makes absolutely no sense when solder paste is readily available and all I use is a cheap toaster oven (and technique).
    ..
    But I wonder how much less efficient the heat transfer might be leaving the hole there.
    It was only there as a hand-solder assist, and it certainly removes copper and thermal paths in exactly the wrong place, so yes, it would be best removed.

    4 layer PCB will add much more thermal spread effect, and lower the peak die temperature too.

    A minor suggestion : you could annotate P2 as U1 as that is the primary chip, then FLASH as U2, and EFM8 as U3, Si5351A as U4 etc ?
  • jmg wrote: »
    It was only there as a hand-solder assist, and it certainly removes copper and thermal paths in exactly the wrong place, so yes, it would be best removed.

    4 layer PCB will add much more thermal spread effect, and lower the peak die temperature too.

    A minor suggestion : you could annotate P2 as U1 as that is the primary chip, then FLASH as U2, and EFM8 as U3, Si5351A as U4 etc ?

    4 layer I can do anytime but 2 layer is cheap to test out and redo and 2 layer has proved itself with the original. But 4 layer is a option that I can produce anytime once I am happy with the functionality of the 2 layer prototypes.

    This was the first print I did of the 3D gerbers for this pcb so there were quite a few cosmetic details that have since been edited such as tenting vias, some additional caps were added, and of course moving some of the designators/values from a mechanical layer to the silk screen.

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  • jmgjmg Posts: 13,782
    ... some additional caps were added, and of course moving some of the designators/values from a mechanical layer to the silk screen.
    Looks like there is room to add a optional resistor from TCXO pin 1 to P2 Pin 32, or Vcc, to support VCTCXO or OE.TCXO (no pullup) options ?

  • Like your approach of the 6 pin footprint for the USB protection Peter. Can't make it out clearly where this pin 4 trace is currently going but if you can have the TPS22919 N/C pin 4 SMD pad optionally getting over to VIO on your board using a solder jumper for example that then is very flexible as it allows multiple uses of this footprint. E.g. you could populate and use the TPS22919 part for USB protection, or fit a simple zero ohm resistor / wire from pin 1 to pin 6 to save cost, or instead fit a polyfuse or Schottky diode from pin 4 to pin 3 for back powering wifi modules fitted to the prop plug header at the top of the board. Maybe some enlarged pad space nearby for supporting 1206 size parts would help achieve it even more.

    Another option I was wondering is if the outer duplicated ground (-) pin at the prop plug powering end could just be wired to the 3.3V right under it, then it could bring out 3.3V directly, though it may be safer to just keep it as a ground point in case cables get plugged in the wrong way for example. You wouldn't want to feed 5V into the P2 3.3V directly by mistake.
  • I can't see the sense in using a bully expensive imprecise polyfuse when for 19 cents i can have a compact precise controllable load switch which i also used for the SD too.
    I will look at the other suggestions when i get back but i hope to send it off by Monday at least. They are cheap enough that i can afford to make changes and even order 4 layer when i know it's right.

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  • What's the VSD pin, is that the switched rail you refer to?
  • Yeah, wow if only 19c just stick with it. Didn't realise it was so cheap. I guess it may even allow back powering of VIO though its internal body diode if it's an N-ch FET.
  • I will post the schematics so you can also make sure i haven't messed up. VSD is VB that is switched to the SD. VSD only gets interrupted on a reset or initialisation to ensure the card does not get locked into a state.

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  • ok thats a great feature. Good idea
  • Here are the schematics and a screenshot of the pcb. See if your eyes can pick something I missed or something that won't work properly. If I don't send this off until Monday then I might cobble together a HyperRAM+ESP slice for mounting directly onto the P2D2 and if I have enough time I will get a motherboard done too.
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  • jmgjmg Posts: 13,782
    Here are the schematics and a screenshot of the pcb. See if your eyes can pick something I missed or something that won't work properly..

    Cosmetic, but P15 has a spurious trace under P2 - I see also on P47, so maybe deliberate for some reason ? Fill issues ?
    Is it my eyes, or are the corner fingers on the P2 wider than the other fingers ?
    Is the large hole meant to still be under P2 ?

    Footprints for XO1 and X1 could be made a little more universal, and possible to hand solder, with larger pad areas, to allow smaller and larger packages ?
  • Those spurious traces are actually just a quick way of damming polygon pour in that area.
    Well spotted too with the corner pads, they are a little wider and it's a trick I've implemented for those times when I have to fix up bridges and sometimes run them off to the end pins and I find this wider pads help to collect the excess solder :)

    Seeing though that I have all these components crammed in together on a 2 layer board I still need the space between for ground and connections in general :) So if someone wants to hand solder a crystal they are always welcome to use the big through-hole pads near the U3 designator. If though I get rid of the crystal of the TXCO I can have larger pads.


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  • Peter can I grab the outline dimensions from you please?

    Can I assume they're unlikely to change from this point forward?
  • jmgjmg Posts: 13,782
    edited 2019-04-26 - 08:26:28
    ... So if someone wants to hand solder a crystal they are always welcome to use the big through-hole pads near the U3 designator. If though I get rid of the crystal of the TXCO I can have larger pads.

    I was also meaning to grow the pads inwards too, to allow smaller packages like the 1.6 x 1.2mm TCXOs & xtals
    Nice to have, would be support up to 5.0 x 3.2 size, to include the sub ppm Murata parts, but that may be getting tighter ?
    My earlier flexi-footprints overlaid 3 sizes, but another idea that looks viable, and is less 'cluttered' is to make a rotated finger one. (this has 20 deg spun fingers) & does 5x3.2 down to 1.2x1.6mm


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  • @jmg,
    Nice idea, but if Peter doesn't stop soon, we'll have the next silicon in hand and no pcbs!
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  • Don't forget that all these files are available through my various links or via the Tachyon Dropbox but here is a link to the current Gerbers.

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  • jmgjmg Posts: 13,782
    Yanomani wrote: »
    btw, Four P2D2 pcbs fit within the P2-eval pcb size with room in the center.

    It makes me wonder...

    If P2D2 layout could be easily expanded, at the longer sides, with paired connector footprints, crafted to exactly match P2-Eval...
    ...

    On the topic of connector options, another compatible connector to look into would be the RaspPi.
    There are nice KeDei LCD modules available that use 128MHz SPI and a subset of the 40 pins. They stuff just 10w (SPI) and 4w (i2c) way female headers.
    See images here
    https://www.ebay.com/itm/3-5-TFT-LCD-Touch-Screen-Display-128M-SPI-Case-For-Raspberry-Pi-3-B-Zero-W/323407226634
    and this one includes a case and small fan
    https://www.aliexpress.com/item/32918104361.html?productId=32918104361&productSubject=New-3-5-inch-128M-SPI-60Hz-TFT-LCD-Display-Touch-Screen-ABS-Case-Fan-Heat

    The proposal would be to match just that LCD Module subset pinout, as that looks practical on P2D2. 100% map of all pins is not practical, as P2D2 has 32 IO
    RaspPi pinout used


    Here it is in pictures, top 40p is Pi, and lower is current P2D2 pin mapping.
    RHS VCC.3v3.GND need minor looking pin-swaps, and SDA1,SCL1 could be P32,P33
    LHS swaps 2 GND pin mappings, and can then pickup SPI1 mappings. Possibly one of the 2 x 3v3 moves to pin24 ?
    That leaves just extra GND on Pi vs P2D2, all other pins are compatible, and the useful interface pins are all mapped. GND pins are disabled in P2 code, if someone uses full 40 pin connect map.

    Being able to 'drop-on' LCDs from the huge Pi eco system, would be great for P2 users.
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  • jmgjmg Posts: 13,782
    .. and here it is, swapped and routed, now P2D2 can be Pi-LCD-compatible :)

    This looks to work fine on lower P0..P31, and routes physically ok on P32..P63, but there is an overlap of the SPI pins, if I do a simple sequential peel-off. (ie pin ordering based)
    Pi_MISO1 maps to P2_P59FI, so to avoid LCD conflicts during P2 Boot, another map may be needed ?
    One choice would be to map CLK,SI,SO by name, and have separate CS_FLASH and CS_LCD, which is easy to explain ?
  • jmgjmg Posts: 13,782
    edited 2019-04-26 - 23:21:14
    ..and here is an alternate routed pin-map, that maps parallel connected CLK,SI,SO by name, and has separate CS_FLASH (P61CS) and CS_LCD (P57), & leaves P62TX, P63RX out of the LCD mix.
    This allows a Pi-LCD to share with Flash. ( and I guess SD is ok ?)
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