P2D2 - An open hardware reference design for the P2 CPU

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  • jmgjmg Posts: 13,472
    Just going through a checklist now that I am really going to get the P2D2-R2 design sent out this week..

    I think you already have 5m x 3.2mm Oscillator footprint support ?

    These are a new range of higher end Oscillators, for another price/performance point.
    https://www.murata.com/search/productsearch?cate=cgsubCrystalOscillators&scon=productionStatus;0_avairable@In Production&rows=50&sort=d_nominalfrequencydisp&realtime=1
    come in both Clipped Sine and CMOS, and in VCTCXO options too, which means a DAC connection to the Osc Pin 1 could be useful to add ?

    Looks like P32 passes right by, so a 0402 solder bridge there could cover that ?

  • I'm placing a SI5351A-B-GT clock gen with a tiny 10ppm crystal on the board as an option to the standard 2520 oscillator. I am using P58+59 for I2C data so I will run some checks before committing.

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  • jmgjmg Posts: 13,472
    I'm placing a SI5351A-B-GT clock gen with a tiny 10ppm crystal on the board as an option to the standard 2520 oscillator. I am using P58+59 for I2C data so I will run some checks before committing.

    That sounds very flexible :)

    Attached is a layout I did for Si5351A that allows XTAL or Oscillator drive, into Si5351A, from TCXO.VCTCXO oscillators.
    That allows the PLL of the Si5351A to have the precision of a sub-ppm TCXO.
    The Murata link I gave above, includes 26MHz and 25MHz sub ppm oscillators, in clipped sine.

    On our last lscc order, I added some of these
    https://lcsc.com/product-detail/SMD-Oscillators-XO_KDS_DSA221SDN-26MHz-2-8V-2ppm-40-85_DSA221SDN-26MHz-2-8V-2ppm-40-85_C132298.html
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  • Peter JakackiPeter Jakacki Posts: 8,296
    edited 2019-04-15 - 08:24:42
    Here is the latest schematic for the new P2D2. It is still being updated but it should give you an idea of what to expect. There's still some fiddling to do with the circuit including the oscillator options. The Silabs micro will probably do some smart resetting so that amongst other things any DTR style reset will always cause it to boot serially and ignore the Flash and SD.

    I like the Si3531A clock option because the chip is cheap and so are the crystals but I'm not sure where best to run the other two clock outputs. I will probably use resistors to connect these to the closest I/O which at present is P32, P33.

    What is the best arrangement for HyperRAM? My HyperRAM board will be a thin pcb that sandwiches onto the back of the P2D2 so it will probably only span a small section of the P2D2.
    P2D2r2.png

    The power section can use an MPM38111 for 1Ax2 outputs or an MPM38222 if we actually really needed 2A although I am using the 2A version on the prototypes. Because this regulator is adjustable I can boost up the 1.8V supply if needed but the main purpose is so that I can pre-regulate into a dual 3.3V LDO to deliver a clean output at fairly high efficiency still.

    P2D2PWR.png

    PCB layout will be posted in the next day or so and I will get this artwork sent off this week which means that I can have pcbs next week and I still have about a dozen P2-ES chips I can use.
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  • jmgjmg Posts: 13,472
    .... There's still some fiddling to do with the circuit including the oscillator options. ...

    I like the Si3531A clock option because the chip is cheap and so are the crystals but I'm not sure where best to run the other two clock outputs. I will probably use resistors to connect these to the closest I/O which at present is P32, P33.
    Looking impressive. Will this be 4 layer for better thermal spreading ?

    Can you fit an AC coupling option from Oscillator to XA on Si5351A ? - that allows a TCXO (26MHz) to drive the Si5351A, for very precise synthesised values.
    Also Pin 1 on the Oscillator, is Voltage Control on VCTCXO models, so routing that to a P2 pin, allows DAC to control frequency.

  • Peter, it will be nice if the Si3531A's SCL/SDA pins will be routed to both the P2 and the monitor chip

    BTW: what are RSTIN, DTR and XIN on the monitor for? Where are they connected?
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  • I am hoping that SCL/SDA will be on P58,59 and I see no reason why not since I2C not only needs a valid start condition and address but it also filters any glitches which is what these signals would look like when operated in SPI mode. So the monitor can communicate with the P2 and vice-versa via I2C so that the monitor could load the clock gen although I don't think that will be necessary. The clock gen has OTP that can be programmed to load into its registers at reset so that I can set this up when it is assembled and tested to output a clock automatically. If I write some routines for the P2 then it can also setup the clock gen too.

    As for the DTR signal I shouldn't need it directly as the USB serial firmware will be enhanced to automatically generate a nice reset pulse and also make sure that the P2 doesn't boot from Flash/SD when loading from serial. But the RESn is also an input to the monitor so that it can detect both the very short pulses from a PropPlug or the manual reset button which can be used to force a particular boot mode. As for the XIN on the monitor that may not get connected since it would have to run across the board but the idea was so that the monitor could possibly drive the XIN of the P2 if necessary since the Silabs chip has a 1.5% 48MHz precision oscillator that could replace other clocking options (as an option). But the monitor chip also measures the temperature and can also report actual A/D levels etc.

    BTW, the DTR signal was originally meant to monitor the DTR of a cheap USB serial converter and generate the reset pulse but since I upgraded the monitor to a USB version, there shouldn't be any need for that now.

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  • TonyB_ wrote: »
    How about HDMI output? Are particular pins recommended for this and do they need special treatment, such as equal trace lengths and other design considerations?

    Bump.
    Formerly known as TonyB
  • TonyB_ wrote: »
    TonyB_ wrote: »
    How about HDMI output? Are particular pins recommended for this and do they need special treatment, such as equal trace lengths and other design considerations?

    Bump.

    The pins to the center of the pcb are very short and probably suitable for balanced HDMI signals but I haven't really followed the HDMI threads to even begin considering what else I might have to allow for. Perhaps someone can make suggestions bearing in mind that the P2D2 is a module designed to be used standalone in some cases, but mostly as a "big chip", a bit like a Stamp, that can be plugged into an application specific board.

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  • roglohrogloh Posts: 1,059
    edited 2019-04-15 - 23:54:04
    TonyB_ wrote: »
    How about HDMI output? Are particular pins recommended for this and do they need special treatment, such as equal trace lengths and other design considerations?

    @TonyB_, when I can hopefully get my hands on one of these P2D2's I want to try HDMI output from this P2D2, at least experimentally. My own motherboard uses an HDMI connector on P2 pins P40-P47 which are close to the middle of Peter's board and of shorter length. Ideally each differential pair would have the same trace length and impedance etc, but it is slightly less important over the 4 pairs and more important between the two wires of any pair. My own board is not following ideal differential layout either so if it works along with the P2D2 as is then I'd suspect it is already reasonably robust. And even though not it's obviously not recommended, IIRC Chip was able to get HDMI up over some flying leads, so there's probably some wiggle room there.

    Peter, I wonder if the SDON signal should have an optional pulldown resistor SMD pad in case there are situations where the monitor micro is not fitted and you still need to use the SD card (or some other way to bypass the P-FET entirely such as a solder pad in parallel between its source and drain)? Do you envisage operation without the monitor micro being possible?
  • jmgjmg Posts: 13,472
    jmg wrote: »
    Can you fit an AC coupling option from Oscillator to XA on Si5351A ? - that allows a TCXO (26MHz) to drive the Si5351A, for very precise synthesised values.
    Also Pin 1 on the Oscillator, is Voltage Control on VCTCXO models, so routing that to a P2 pin, allows DAC to control frequency.
    If room is tight, an alternative layout would be to AC couple the clipped sine TCXO into the Si5351A, and remove the Xtal option.
    26MHz TCXOs are quite cheap (VCTCXO here is 25c/100), for good ppm levels. I have 30 of these & can post you some if you want ?

  • jmg wrote: »
    If room is tight, an alternative layout would be to AC couple the clipped sine TCXO into the Si5351A, and remove the Xtal option.
    26MHz TCXOs are quite cheap (VCTCXO here is 25c/100), for good ppm levels. I have 30 of these & can post you some if you want ?

    Sounds like a plan but aren't these 2.8V parts? I see that the recommended max is 2.94V although the absolute max is 4.6V so it would seem that I won't kill it at 3.3V but it might not operate within spec.


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  • jmgjmg Posts: 13,472
    Sounds like a plan but aren't these 2.8V parts? I see that the recommended max is 2.94V although the absolute max is 4.6V so it would seem that I won't kill it at 3.3V but it might not operate within spec.
    Strictly yes, but that's to allow some decoupling drop I think, and they calibrate at 2.8V, but the Vc tolerance is very good.
    The one I wired up here, has 3v3 and needed 1.575V on the trim pot Vc to nail down to 26.000000MHz, which is very close to 50% on Vc
    P2 can drive from clipped sine fine at 26MHz and is ok 38.4MHz, but it is rolling off at 38.4MHz, 48MHz is probably tops.. (they have Zo of ~ 180 ohms)
  • I am hoping that SCL/SDA will be on P58,59 and I see no reason why not since I2C not only needs a valid start condition and address but it also filters any glitches which is what these signals would look like when operated in SPI mode. So the monitor can communicate with the P2 and vice-versa via I2C so that the monitor could load the clock gen although I don't think that will be necessary. The clock gen has OTP that can be programmed to load into its registers at reset so that I can set this up when it is assembled and tested to output a clock automatically. If I write some routines for the P2 then it can also setup the clock gen too.

    As for the DTR signal I shouldn't need it directly as the USB serial firmware will be enhanced to automatically generate a nice reset pulse and also make sure that the P2 doesn't boot from Flash/SD when loading from serial. But the RESn is also an input to the monitor so that it can detect both the very short pulses from a PropPlug or the manual reset button which can be used to force a particular boot mode. As for the XIN on the monitor that may not get connected since it would have to run across the board but the idea was so that the monitor could possibly drive the XIN of the P2 if necessary since the Silabs chip has a 1.5% 48MHz precision oscillator that could replace other clocking options (as an option). But the monitor chip also measures the temperature and can also report actual A/D levels etc.

    BTW, the DTR signal was originally meant to monitor the DTR of a cheap USB serial converter and generate the reset pulse but since I upgraded the monitor to a USB version, there shouldn't be any need for that now.

    I2C require pullups on both lines. It will be nice if this can be 2 dedicated P2 pins that match the EFM8 xbar SMB0 peripheral configuration. It support multi-master mode. I would like to port my multi-master driver to P2. The two (P2 and EFM8), beside speaking between them, can control in this way also other components on the motherboard.

    It will also be nice if the EFM8-SPI0-Pins match flash pins, so that it can be eventually programmed through the USB even with halted (hold in reset) P2 (depending on EFM8 firmware of course).
    ... Perhaps someone can make suggestions bearing in mind that the P2D2 is a module designed to be used standalone in some cases, but mostly as a "big chip", a bit like a Stamp, that can be plugged into an application specific board.

    Hi @Peter Jakacki. I gave a look at the EFM8UB3 and Si5351A datasheets.
    It is a 51 core, nice ... I have a lot of code from my past for it. A lot can be done in 40K and moreover it comes with a usb boot-loader.

    I have some suggestions/considerations:
    - the 3 clocks from the Si5351A: CLK0->P2, CLK1>EFM8-P0.3(ExtClk), CLK2 to P2D2 pin (to clock possible other motherboard elements)
    - supply the VREGin pin through 2 schotky diodes: 1 from USB 5V supply, the other from the MPM38111GR-VIN, to always power the monitor.
    - if you can pls use a qfn24 part. Avoid using EFM8 debug pins for P2 interconnection, if necessary it can be done (bridged) on motherboard. Route the unused pins to P2D2 pins.. . It doesn't matter if the (new) module will have one/two pins/side more.
    -- the EFM8, while in snooze mode have its CLU, and some other peripherals active. Many things can be done.
    -- eventually have a look on EFM8 datasheet p.36, where they consider a USB connected while the chip is unpowered.
    -- route USB-5V also to P2D2 dedicated pin and connect EFM8-P2.1 to VBUS (using the above p.36 care). In this way the motherboard can have some additional components to eg charge a battery from USB (EFM8 controlled as it is aware of connection)
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  • Peter JakackiPeter Jakacki Posts: 8,296
    edited 2019-04-17 - 04:04:23
    @dMajo - Yes, all good points and some I had already covered in the process such as a pull-down on the SDON signal etc.
    I have run the other two clocks to through-hole pads ready to interface to my HyperRAM board that gets surface-mounted onto the back.
    P57 is now SDA and P56 is SCL but I still have to route them to the monitor somehow. Maybe I do need 4-layer but I've almost got it all in on two layers with generous ground and power. One concession is that the header pins for I/O power next to the +5V VCC is now the VIO from the switcher which is about 3.6V although 3.3V is still available near the USB end and switched SD power near the reset pin.

    Since I have the EFM8UB3 I don't need access to the chip's reset so this is left free but P2.0 which is also the C2D line is used to switch the SD power. Depending upon what I may like the monitor to do it, it's SPI port may be optimized to talk directly to Flash or SD or simply emulate Flash but either way I'm sure there won't be any problem bit-bashing as a master.

    As for USB power I find just shorting it across to the +5V works but I will allow for various options (as routing permits).




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  • jmgjmg Posts: 13,472
    dMajo wrote: »
    ...
    I have some suggestions/considerations:
    - the 3 clocks from the Si5351A: CLK0->P2, CLK1>EFM8-P0.3(ExtClk), CLK2 to P2D2 pin (to clock possible other motherboard elements)
    CLK2 to P2D2 pin is a good idea, as that can also be used as a useful (async) test signal into P2.
    CLK1 to EFM8 is nice to have, if routing permits, but the EFM8 does USB fine with the on-chip RC OSC ?
    maybe having accurate UART baud could be useful ? Any other use cases ?
    dMajo wrote: »
    ...
    if you can pls use a qfn24 part. Avoid using EFM8 debug pins for P2 interconnection, if necessary it can be done (bridged) on motherboard.
    Being able to 'get at' the C2D pins would be useful, should the bootloader get accidentally clobbered :)


  • Hi Peter,
    although not able to follow P2 development In depth or contributing something useful I'd appreciate a P2 eval or developer board with an ethernet socket. Maybe the integration of the wiznet5500 can be foreseen in any way or in a future design.
    The only thing I currently can do is passively read what is growing and permit that my best wishes are with this project and this extraordinary community.
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  • dMajodMajo Posts: 742
    edited 2019-04-17 - 17:07:23
    ...
    I have run the other two clocks to through-hole pads ready to interface to my HyperRAM board that gets surface-mounted onto the back.
    ....
    Pls route one clock to the monitor EXTCLK pin. I think that one clock signal out of P2D2 is enough for external components.
    Or if you need 2 clocks externally than route CLK0 to both the P2 and the monitor EXTCLK. In this way the EFM can monitor the clock and some communication can be done with P2 (through the already available interconnected pins eg IIC) to allow the P2 to switch from the internal OSC to external CLK.
    The activity on the I2C line can also trigger a watchdog in the monitor.
    ...
    P57 is now SDA and P56 is SCL but I still have to route them to the monitor somehow.
    ...
    This is OK. Of course P56/57 are also available on the P2D2 side pins to extend the bus externally of the module
    ...
    Depending upon what I may like the monitor to do it, it's SPI port may be optimized to talk directly to Flash or SD or simply emulate Flash but either way I'm sure there won't be any problem bit-bashing as a master.
    ...
    bit-bashing ... I don't know .... perhaps .... let say yes .... depending on other things the monitor have to do.
    Anyway the smartest choice is to match the SPI0 peripheral to the FLASH chip, and eventually bit-bash the SD.
    The SD can eventually be extracted and programmed through any laptop/pc card-reader. The flash can't be de-soldered and it is harder to program without specific tools. Here the monitor's USB direct flash access can help. Not only for firmware, it can be only for parametrization in a specific flash area and/or data reading (let think on a power hungry device/data-logger where just by connocting the USB you power only the monitor and the FLASH and thus read-out the data .... Everything depending on the monitor's firmware of course)
    ...
    As for USB power I find just shorting it across to the +5V works but I will allow for various options (as routing permits).
    In regards to the previous point ideally the USB/EFM/FLASH power will be done like this:
    (P2D2.VIN>---(DS>---(EFM.VREGIN)---<DS)---<USB.VBUS>---(R22K1)---(EFM.P2.1)---(R47K5)---(GND)
    
    (EFM.VDD>---(FLASH.VDD)
    
    connecting EFM.P2.1 through resistor divider like shown on its datasheet p.36
    ...
    Since I have the EFM8UB3 I don't need access to the chip's reset so this is left free but P2.0 which is also the C2D line is used to switch the SD power. ...
    That's fine, but both the resets (P2.RST and EFM.RST/C2CK) should be available esternally of the P2D2 module.

    It also doesn't matter that the C2D powers the SD too. The debug signals are only for emergency (should the bootloader goes away) and/or for debug, during development, where the P2D2 (and thus the SD) can be unpowered and the EFM supplied through the USB port.
    It is only important that the two debug pins are available somewhere on the P2D2 PCB.
    It can be on the side pin strips or just 2 pads spaced 0.1 inch somewhere where, if needed, two pins (like jumper) can be soldered. In the latter case, since the EFM.RST shares the debug CLK only the P2.RST should be available on side pin strips.
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  • Peter JakackiPeter Jakacki Posts: 8,296
    edited 2019-04-20 - 02:56:57
    When I couldn't get back to sleep in the wee hours of the morning I got up and checked the forum and it was still too hard to solve a simple code problem so I moved onto finishing off the last 1% of my pcb. There were about 6 tracks that I just couldn't seem to route after I had already routed 6 that seemed impossible. The problem looked in"track"able and since I was considering going to a 4-layer board to overcome it I decided I would get a bit more pushy. So I pushed through the ground plane on the bottom side of the board with these objectives still in mind:
    1) Don't use anything smaller than 0603
    2) Double-sided only
    3) Components on top side only

    Well, after I got pushy I found a way and while I still need to go through and trim up some clearances and improve ground and power in some places the design looks done. However I still need to review the schematic to make sure that this configuration will work the way I want.
    Notes: The oscillator options are more limited yet more flexible. I can either have a 2520 crystal direct to the P2 or use the Si5351A with a 25MHz crystal. If it doesn't mess up the pcb I will consider some TXO options (maybe) and also route the 2 clock outputs to the edge somewhere.

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  • Cool, getting close now! Those last nets are always the hardest to squeeze in aren't they? :smile:

    I wonder if the I2C lines now attached on P2 pins 56/57 can still be used for other purposes? On my own board I had assigned them for USB signals like the P2-ES board does, though I probably could reroute them with fairly close pins for SDA/SCL on my board with another PCB spin. Seems I might have to respin my own board now anyway as you've put in those 3.6V VIO pins at the regulator end and I'd sort of used them to access 3.3V. :frown: What was the reason for these new VIO signals? Is that to allow some optional external lower noise (non-switching) regulators to source into the onboard LDO, or for something else?

    The regulator caps look tightly packed down there, would it be very hard to hand solder them? Maybe the pad's silk overlay outline just makes it look closer.
  • Looking good Peter :smiley:
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  • Hi Peter

    You've just teached me how many angels could fit in a pin head!

    Man, it's tight...
  • It's much easier to paste and place, then pop them into the toaster oven than it is to hand soldered. Besdies, the trick to hand-soldering when you need to do it is not to use a really fine tip but one that is flat and can maintain its heat so that you can easily heat the joint and melt the solder.

    I tend to use I2C bus for RTC chips and many kinds of sensors so certainly these pins will be reused. The monitor chip is also a slave chip along with the Si5351A but the monitor can also become the master, especially when it holds the P2 in reset.

    Part of the reason for packing the passives in against the regulator is simply to do with keeping the tracks as short as possible for stable switching operation. The dual LDO straddles the 1.8V supply so it made sense to branch each one off to the A and B port pins. VIO though will be around 3.6V and lends itself to being fed off-board where it an LDO can convert this efficiently but the 3,6V is not too high that you can't connect it directly to 3.3V chips.

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  • jmgjmg Posts: 13,472
    Notes: The oscillator options are more limited yet more flexible. I can either have a 2520 crystal direct to the P2 or use the Si5351A with a 25MHz crystal. If it doesn't mess up the pcb I will consider some TXO options (maybe) and also route the 2 clock outputs to the edge somewhere.
    It looks like there is room for a (VC)TXCO outside the Si5351A, the clipped sine ones need a AC coupling cap into Si5351A and maybe there is room for an optional jumper under the Si5351A to allow a TXCO to feed direct to P2 (when Si5351A is not fitted) ?

  • VIO though will be around 3.6V and lends itself to being fed off-board where it an LDO can convert this efficiently but the 3,6V is not too high that you can't connect it directly to 3.3V chips.

    Thanks Peter. Yes it would be quite good for me to try with 3.6V feeding the 3.3V devices I already have on the VIO pins. Then I can at least begin debug of my existing first PCB without doing another respin right away. I sort of expected a respin anyway as I have to resolve some thermal issues but it would be pretty good to find all my other gotchas first. Hoping some of these thermal issues may be assisted with a new P2 rev lower power draw too.
  • Here's the latest artwork which now allows for a TXCO option for the Si5351A. The artwork is taken from a negative of a screen shot and then equalized to make the colors pop but the component values are actually on a mechanical layer as are most of the designators.

    The left hand edge of the pcb which has the optional reset switch, LEDs, and coms + power pin headers is designed to be snapped off if not needed but I will probably leave it on as standard. Power and activity LEDs can be mounted either side to suite.
    P2D2R2-2.png
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  • Really nice. Now, when can I pre-order and pay for an assembled unit?
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  • jmgjmg Posts: 13,472
    Here's the latest artwork which now allows for a TXCO option for the Si5351A.
    Looks good.
    There may be room for a via on XA, to allow a work-jumper onto XI ?

    Also, could in 1 of the TCXO be made a little larger, to allow a lead to be soldered to jumper to P2.DAC pin for VCTCXO or to Vcc for an OE model, with no pullup.

  • Just wondering... if the P2D2 is ever USB powered does it make any sense to have a polyfuse footprint as well as (or instead of) the 0 ohm resistor feeding into VCC in case of overload conditions. That might at least give some small amount of short circuit protection. Though I do know polyfuses are not especially nice to work with, just ask the Raspi guys.

    Maybe there are better protection options, albeit probably more complex/costly. However a polyfuse is at least symmetric in case you wanted to run power out to the external serial pin header (eg. for ESP8266 module type downloads), though the VIO is probably a better voltage to use then. I noticed there is a small amount of board space left there for some flexible power/protection solutions that may make sense...
  • I suppose I could allow for a 1206 polyfuse since they are a lot cheaper than their smaller cousins. Personally I've never had any problems with USB port power shorting and the only time I wrecked a USB port on a laptop was when I had a serial cable plugged into equipment being tested and then plugging the laptop into power, but that wasn't a short.

    jmg - as I "finish" something functional I'm always tempted to push something else in. But where do we stop? Isn't a crystal option or the Si3531A with either a crystal or TXCO more than just an option? Besides, the new silicon's PLL should be a lot better.

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