P2 documentation

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  • potatoheadpotatohead Posts: 9,577
    edited June 1 Vote Up0Vote Down
    The key thing with time is really understanding what you need vs what you may want.

    Even seemingly simple wants can end up insane complex.

    Equidistant, for example. Why?

    It may be time and date across teams, for example, matter. "Bob touched this last tuesday at noon" (what noon, where in the world?)

    But, "Bob touched this last week, or just last" may well do all you need. And it's way easier.

    The difference between those is, or can be a ton of complexity, particularly if the effort needing a running history is distributed geographically at all.

    Precision, consistency, regularity, coherence, universality, all carry costs on both complexity, and to a degree, resource axis. Maximizing all of those is rarely indicated.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • I didn't realize that. I have read a ton of times "seconds since the epoch" and just believed it, because, well, it made perfect sense. Leave it to committees to take something totally simple and sensible, and decide that it needs to be messed with.
    Particularly patient proactive practice positively predicates practically precise poly-processor Parallax Propeller programming paradigms.

    .
  • As interesting as time stamps are, please don't clutter this thread into oblivion guys.

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  • I'm appending links to the bottom of the shortform datasheet so if anyone has links for gcc, openspin, SD booter and monitor etc, then please post them here in this thread so I can add it to the sheet. I'd like them all visible on the last page for convenience and also to show the support that is already available.
    https://www.dropbox.com/s/mlbr1kcet47aowo/P2 shortform.pdf?dl=0

    BTW, I apologize if I came across a bit gruff but I still like to talk about time stamps, so please start a thread about it. It should be interesting...

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  • potatoheadpotatohead Posts: 9,577
    edited June 3 Vote Up0Vote Down
    Please don't be. This is an important time. Soon I can join you. Fair call Peter.

    I am super stoked over you, Cluso and Chip getting what looks like great work done. Thank you.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: https://forums.parallax.com/discussion/123709/commented-graphics-demo-spin<br>
  • Thanks for the documentation, Peter (not to mention all the other great work you and Cluso have accomplished). Having a thread for P2 documentation sounds like a great idea.
  • Here's a link to spin2gui, which is a GUI for Spin development on P2 (using fastspin and loadp2):

    https://github.com/totalspectrum/spin2gui/releases/latest
  • Yes, a P2 Documents thread is quite timely now that everything is basically frozen. Thanks Peter. I'll post the link for the Monitor/SD later when I get home.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • evanhevanh Posts: 5,913
    potatohead wrote: »
    But, "Bob touched this last week, or just last" may well do all you need. And it's way easier.
    As long as the details are also available.

    I really don't like the new forum's way of displaying the datestamp of posts. It's oriented from current time only. Comparing older post relative to each other is now futile. It just says December 2017 or something for the whole lot. The sense of minutes/hours/days between posts is lost.

    Money is a placeholder for cooperation
  • evanhevanh Posts: 5,913
    They've changed from integers to floats!

    Money is a placeholder for cooperation
  • Peter JakackiPeter Jakacki Posts: 7,868
    edited June 5 Vote Up1Vote Down
    Here's a new pinout based upon the P2 chip artwork. I will be updating my shortform with this. I haven't checked for mistakes properly as yet but I've taken the liberty of shortening the VIO_xx_xx labels to something that isn't such a mouthful and formats well. The orientation of the labels is more in keeping with standard drafting practices (only need to rotate it 90' CW to read all "vertical" text)
    I spot a mistake already :) (updated again with ground pad)
    p2pinout-4.png
    1616 x 1588 - 318K

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  • Hi Peter

    Wasn't (P6063) at pin number 97, the mistake you'd spoted?

    Shouldn't it be V6063 (at least it seems logical to me, based on the names you'd used for the other VIO_xx_yy)?

  • Yanomani wrote: »
    Hi Peter

    Wasn't (P6063) at pin number 97, the mistake you'd spoted?

    Shouldn't it be V6063 (at least it seems logical to me, based on the names you'd used for the other VIO_xx_yy)?
    No, I missed that one but I was hoping someone would look for errors! :)
    Thanks
    I'll update the shortform shortly

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  • jmgjmg Posts: 12,619
    No sign of any text mentioning GND connections ? (ie saying the slug is the GND and must be connected )
  • Excellent work as always Peter. Are you in the wrong employment? Maybe graphics artist might be more suitable???

    Might be time for a spot of color?
    Red for VDD and orange for Vxxxx, yellow for the special pins?
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • To be true, I wasn't looking for any errors (nor mistakes, kindly speaking) at all; I was only trying to be ensured I could see anything at all, given my poor eyes's actual condition! :lol:

    I believe I has seen that pinout, and also your beautiful work so many times, that it became kind of a Spot the Differences game to me, to catch for any mismatches.

    I kinda have it imprinted at my retina's background. Then its easy peasy to me, superimposeing any other image, and doing the compare!
  • jmg wrote: »
    No sign of any text mentioning GND connections ? (ie saying the slug is the GND and must be connected )

    True enough even though it is in the shortform datasheet pinout table. I will have to think how I can add ground pad as a "pin" to the diagram without messing it up.

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  • The table on page 2 of your shortform has pin 50 as VDD, should this be XO?

    What does the TEST pin do if you don't connect it to ground?
    Sapphire
  • Sapphire wrote: »
    The table on page 2 of your shortform has pin 50 as VDD, should this be XO?

    What does the TEST pin do if you don't connect it to ground?

    Good catch, it was correct but I redid the table formatting and a couple of entries got messed.

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  • Peter JakackiPeter Jakacki Posts: 7,868
    edited June 5 Vote Up0Vote Down
    Cluso99 wrote: »
    Excellent work as always Peter. Are you in the wrong employment? Maybe graphics artist might be more suitable???

    Might be time for a spot of color?
    Red for VDD and orange for Vxxxx, yellow for the special pins?

    The trouble with colors is that there is no real control on how they display and print so that sometimes you think that a light red background makes the pin standout but when you print it the text is obscured and the contrast is less than optimal. So colors are great for diagrams but the pinouts have to be clear and legible and correct.

    My first job in electronics they mainly employed me to do manual drafting, you know, at those big drafting tables with those big sliding squares. So I'd have to do all these mechanical drawings but if I had to revise one, I would cheat, much to the disdain of my boss, by photocopying, cutting and pasting, and then photocopying again for a clean copy. I mean, what's the difference? :) They also got me to layout pcbs manually, and I do mean manually, by cleaning the copper laminate and marking up with a dalo pen, then mix up some Ferric Chloride in an agitator with the heat lamp, checking until it looked right, then clean it off and drill and cut and assemble etc.

    But in the early 80's I acquired a Mac XL and a network of Fat Macs along with a "very" expensive Postscript laser printer so not only would I design my PCBs with MacDraw on multiple layers, but I would print onto laser transparencies and submit these to an imaging lab that could do final negs since the print wasn't dark enough to be usable. But the Macs were very useful for documentation too although we didn't have color back then, we could do drawings. There was no way to take a "digital photo" though, something that we take for granted these days, but the results were quite good (for the time). Way ahead of miserable DOS PCs.

    These days I use Linux and LibreOffice Draw/Write etc and Gimp and other FOSS.


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  • T ChapT Chap Posts: 3,903
    edited June 5 Vote Up0Vote Down
    What is the size of the ground pad on the IC. And is all of the ground pad needed to be soldered for heat dissipation or can the PCB center pad be smaller than the IC center pad and allow for other traces (VDD and V0-03 etc) to fit between The main pins and the center pad. It would be nice to at least fit a bunch of vias around the pad to connect layers 2 and 3 to VDD etc.
  • Peter, I like the P6360 naming convention. Much better.
  • All die GND connections are bonded to the exposed pad on the bottom of the package. The pad is 10.3 x 10.3 mm and centered.
  • What does that mean thermally? Can less than the exposed pad be used to attach to the PCB?
  • jmgjmg Posts: 12,619
    edited June 5 Vote Up0Vote Down
    ... (updated again with ground pad)[/img]
    To me, that gnd pad placement looks too much like a special corner pin as placed, it needs to be clear of the package with a looping arrow and the word 'under' or 'underneath' or 'exposed pad' added.
    I would also suggest adding the formal package name, in the fine print of the image - eg like eTQFP100 14x14 0.5mm
    A small image could communicate the real size of the pad too. One example google finds : (no idea if that is 10.3mm PAD ? perhaps not quite ? )
    sv-100-1_sml.jpg

    and I see google finds some dude posted this (hybrid) image - I'm guessing that PAD is 10.3mm ?
    8daeb8a1cf2efd90b252b62ece3b91.png
  • jmgjmg Posts: 12,619
    T Chap wrote: »
    What is the size of the ground pad on the IC. And is all of the ground pad needed to be soldered for heat dissipation or can the PCB center pad be smaller than the IC center pad and allow for other traces (VDD and V0-03 etc) to fit between The main pins and the center pad. It would be nice to at least fit a bunch of vias around the pad to connect layers 2 and 3 to VDD etc.
    T Chap wrote: »
    What does that mean thermally? Can less than the exposed pad be used to attach to the PCB?

    You would need to avoid copper other than ground under the pad (which is where a real image helps) - ie you need a footprint PAD at least as large as the 10.3mm Chip mentions,
    but there is some room left, just not a lot...

  • Maybe not practical for a ring of vias around the pad but hopefully a trace around the pad for VDD to reduce clutter outside.
  • cgraceycgracey Posts: 10,543
    edited June 5 Vote Up0Vote Down
    It helps to have a via array stack for GND under the exposed pad. It needs to connect to a GND plain(s) to spread the heat.
  • jmgjmg Posts: 12,619
    T Chap wrote: »
    Maybe not practical for a ring of vias around the pad but hopefully a trace around the pad for VDD to reduce clutter outside.

    Yes, that likely comes down to how small a via your PCB FAB can support :)

    It would be nicest to have both Core Vdd and IO vdd inside the pads.

    infineon has a series of exposed PAD parts, but none I see go up to 10.3mm - but you get the idea and dimensions here
    https://www.infineon.com/cms/en/product/packages/PG-LQFP/PG-LQFP-100-12/

    You can go slightly wider than 14mm for the pad end, for appx 2mm of tramline space. Might fit vias-to-lower ring, and an upper ring ?
  • Maybe move these OT threads to my PCB thread.
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