Catalina and the P2

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  • evanh wrote: »
    TonyB_ wrote: »
    What happens if there are simultaneous writes to different locations - does or will that work?
    That one's no issue. The RAM is dual-ported so there is no conflict there.
    And can we say for certain yet what will work in the final hardware for different combinations of LUT sharing and simultaneous reading and writing?
    Yes, Chip has it implemented in the FPGA. I've tested it. The read data corruption no longer occurs.

    A little difficult to prove given the somewhat unknown nature of coordinating two cogs but, supposedly, the reading cog receives the new data being written by the writing cog. This will be done with extra mux circuit to copy around the RAM when the two accesses coincide.

    Thanks, Evan. It seems that only simultaneous writes to the same location are uncertain.
    Formerly known as TonyB
  • Just reran the tests with an eye to precisely which timing alignment the new data appears at and am happy that above summary is correct.

    To do a test for simultaneous writes will need more work to compare a read back of each cog ...

    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • evanhevanh Posts: 6,643
    edited 2019-03-10 - 16:00:51
    Bad news. Coinciding data writes from both cogs sometimes corrupt, sometimes okay. Completely unreliable. Don't do it. Find another solution. I actually wonder if it is setting up an electrical fight.

    On a totally unrelated note, something peculiar has shown up with my testing method. The COGATN mechanism seems to have different timings depending on whether it is odd or even numbered. EDIT: I've got bigger differences with other combinations. I'm guessing it's on a hub rotation scheme, like access to the lock bits and cordic.
    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • TonyB_TonyB_ Posts: 1,130
    edited 2019-03-11 - 12:32:19
    evanh wrote: »
    On a totally unrelated note, something peculiar has shown up with my testing method. The COGATN mechanism seems to have different timings depending on whether it is odd or even numbered. EDIT: I've got bigger differences with other combinations. I'm guessing it's on a hub rotation scheme, like access to the lock bits and cordic.

    Does this mean cogs A and B are not in perfect sync after COGATN for A and WAITATN for B? Main interest here is when the cogs are a LUT-sharing pair. What are the differences in this case, if any?
    Formerly known as TonyB
  • I never expected them to be in lock-step exiting COGATN/WAITATN together but I certainly wasn't expecting interval variances. The way to get into lock-step is use a WAITCTx on both cogs - Which is what I've been doing. The WAITATN did acheive what I wanted which was to notify of job complete and data logged for pickup.

    I just happen to be recording the start and finish times for each test. Up until I added the COGATN/WAITATN part, it was very predictably whatever I specified in the WAITCT1 numbers. But that all changed with a WAITATN. The amount of time to completion differed depending on cog order, with a range of eight clocks. The cogs involved were still starting from the same forward marker as before and running identical code on each cog.

    Admittedly, the earlier tests were only of the duration of code running on the receiving cog. It was in effect just verifying that no disturbances occurred when the sending cog modified lutRAM. With WAITATN added it is now measuring the sending cog plus COGATN mechanism instead.

    But the fact that there is changes in the measured interval which are solely depending on which cog is sending and which cog is receiving is enough to make the claim. The eight clock range is somewhat of a giveaway too. I guess this all reinforces that WAITCTx is the precise timing tool.
    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • Okay, there isn't any COGATN issue. It's fine once I did a clean up without all the lutRAM baggage.

    In process I've worked out that the receiving cog exits the WAITATN instruction two clocks after the sending cog exits the COGATN instruction.
    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • evanh wrote: »
    Okay, there isn't any COGATN issue. It's fine once I did a clean up without all the lutRAM baggage.

    In process I've worked out that the receiving cog exits the WAITATN instruction two clocks after the sending cog exits the COGATN instruction.

    Thanks for the info, Evan. Therefore COGATN+NOP in sending cog and WAITATN in receiving cogs synchronizes them. Might be worthwhile adding this to your reference post.
    Formerly known as TonyB
  • I feel the description is concise and clear enough as is. An example should prolly be more complete if wanting to show the effect.
    "There's no huge amount of massive material
    hidden in the rings that we can't see,
    the rings are almost pure ice."
  • I've been doing a lot of reading on the P2, and I'm ready to start coding a new version of Catalina ... but one thing I have yet to find is a repository of P2 objects, similar to the old P1 OBEX. Is there such a thing? I know there is a P2 Github repository - https://github.com/parallaxinc/propeller - but it doesn't seem to contain much yet.

    I believe that many of the simpler P1 objects would work on the P2 with just a few minor tweaks and a recompile ... but I can't find if this has been done yet or not.

    Am I just looking in the wrong places? There's a lot of stuff I've yet to read on the P2, and I'm probably still missing a lot!
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • RossH, as of yet, there is no Obex for the P2. I don't know if we even have the context for one, yet.
  • Thanks, Chip. I will probably be spinning off a few P2 versions of P1 objects as I work on my Catalina update, and I see a few objects being developed in individual threads (VGA drivers etc), so maybe this is a good time to start one?
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • RossH wrote: »
    Thanks, Chip. I will probably be spinning off a few P2 versions of P1 objects as I work on my Catalina update, and I see a few objects being developed in individual threads (VGA drivers etc), so maybe this is a good time to start one?

    Maybe it is. I don't know what to do about it, though, other than to ask whoever at Parallax manages the current Obex.
  • If you build it, they will come ... :)
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • @RossH,

    nice that you show up again, even if you needed to get sick to do so. The current development around the P2 is sort of exploding, @ersmith is coming out with new versions almost daily, It is hard to keep up.

    Sadly there seems to be no one at parallax to collect and publish all the stuff in one place, like me Parallax is new to git and GitHub, so I do not complain.

    We lucky guys who could get one of the evaluation P2's are just hammering them to find flaws and most stuff is still just in the forum pages, the Parallax Link you provided is needed and cool, but not yet used by any of the contributors.

    So you basically have to hunt down the newest versions of all dev tools and the currently best space to do so is @DavidZemon's TeamCity Build Server at http://david.zemon.name:8111/?guest=1

    Enjoy!

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • Hi Ross,

    Did you manage to get some hardware?

    If not I have some Parallax A7 and A9 Fpga boards that could be sent to you, if useful.

    These would let you work on the latest FPGA image for the silicon currently being taped out.

    regards
    Lachlan
  • Hi Lachlan

    Thanks for the very kind offer, but Chip has already sent me a P2-ES development board. It has arrived at my PO Box but I only go into town once a week, so I haven't picked it up yet. Should get it tomorrow.

    In the meantime, I have been using my DE-Nano to just just get some basic familiarity and try out a few things. But the Nano is quite limited - e.g. only one cog, not much RAM and the TAQOZ in the boot ROM doesn't work on it (apparently this is because it has no CORDIC functions).

    One thing I have learned is that it is currently very difficult for newcomers to get started on the P2. There are very few introductory documents around, and you have to read a lot of separate documents, and also trawl through dozens of forum threads - many of them years old, and containing hundreds of pages of out-of-date information - just to get enough information to get started :(

    I'm sure things will improve once the silicon has stabilized, but it has been hard going, even for someone like me who is very familiar with the P1. An outsider would have no hope at this stage. I wonder if any of the P2 gurus here realize just how difficult it currently is?

    Ross.
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • RossH wrote: »
    One thing I have learned is that it is currently very difficult for newcomers to get started on the P2. There are very few introductory documents around, and you have to read a lot of separate documents, and also trawl through dozens of forum threads - many of them years old, and containing hundreds of pages of out-of-date information - just to get enough information to get started :(

    I'm sure things will improve once the silicon has stabilized, but it has been hard going, even for someone like me who is very familiar with the P1. An outsider would have no hope at this stage. I wonder if any of the P2 gurus here realize just how difficult it currently is?

    Ross.

    WB Ross!

    It's been extremely difficult for me to get started with the P2 as well. I've saved the Parallax Propeller 2 Documentation v32 and Parallax Propeller 2 Instructions v32. Peter's P2 repo is a great place to dig for example code. Quite a wonderful chip but the p2 manual is going to be it's own monster.
  • Ha!

    Just got my first Catalina C program compiled and running on the P2! :)

    Still a long way to go - this first version is really just a hack of the P1 compiler, and it makes very little use of the new P2 facilities - but at least I can now start having some fun!
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • Congrats Ross! That must be exciting

    What level of C support are you aiming for (C89, 99 etc) - Similar to P1?
  • Yes, initially it will be exactly the same as the P1 version of Catalina - i.e. a C89 compiler with some C99 additions.

    There are some compilers based on LCC that implement compatibility with later ANSI C versions ... I started to look at a few of them. Maybe one day I'll add some of them to Catalina. However, there is so much work to be done just reproducing everything that the P1 version of Catalina could do that I wouldn't hold my breath if I were you! :)
    Catalina - a FREE ANSI C compiler for the Propeller.
    Download it from http://catalina-c.sourceforge.net/
  • Go, RossH!
  • I can see you’ve been busy Ross. Nice to see you back on the props :smiley:
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
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  • RossH wrote: »
    Just got my first Catalina C program compiled and running on the P2! :)
    Congratulations! That's great progress.

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