- Announcement about May 10th, 2018 update and your password.
sodor-spinal a RISC V core in SpinalHDL.
sodor-spinal is my attempt at creating my own RISC V processor core for FPGA.
As I have never attempted to create any kind of processor in hardware before sodor-spinal is about as simple as I could imagine making such a thing. It is based on the Sodor 1-Stage RISC V design that students build in their CS/EE Computer Architecture courses at Oakland, Berkeley, etc. Which is nicely described here: https://passlab.github.io/CSE564/notes/lecture08_RISCV_Impl.pdf
Rather than use Verilog or VHDL sodor-spinal is written in SpinalHDL. SpinalHDL is a hardware description language created by Charles Papon and based on the Scala language. Actually, more correctly, SpinalHDL is just Scala library, the design you create with it is just Scala code that uses the Spinal library. This is not exactly a translation of Scala to Verilog but rather when the Scala code is run in magically generates Verilog. If you prefer VHDL it can do that as well!
The upshot of all this is that writing SpinalHDL is much easier than Verilog or VHDL, a lot less ugly, and you can use all the power of a proper programming language to create your designs.
SpinalHDL is well documented here: http://spinalhdl.github.io/SpinalDoc/
sodor-spinal is mostly complete but has yet to be tested under simulation let alone get anywhere an FPGA.
If anyone is interested in kicking the wheels of Sodor source and installation/run instruction are here: https://github.com/ZiCog/sodor-spinal
This is the basic design it's aiming for:
None of this is very Parallax related, unless we want to mix it up with a P1V, but who else can I talk to about such things? Anyway, it's Chip's fault for getting us all interested in FPGA