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Full-chip integration at On Semi

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  • Heater.Heater. Posts: 20,832
    edited May 8 Vote Up0Vote Down
    kwinn, I like the Roman Numerals, "PROP II". There that is my contribution to this "bikeshedding" discussion.

    koehler,
    ...what does M0/M4 mean, or Risc V?
    Since you asked, "RISC V" is the fifth incarnation of the RISC design from the CS group at UC Berkeley since 1980. From the "The RISC-V Instruction Set Manual":

    "The name RISC-V was chosen to represent the fifth major RISC ISA design from UC Berkeley (RISC-I, RISC-II, SOAR, and SPUR were
    the first four). We also pun on the use of the Roman numeral “V” to signify “variations” and “vectors”, as support for a range of architecture research, including various data-parallel
    accelerators, is an explicit goal of the ISA design."


    Seems they had a desire to distance themselves from their RISC history with some funky names for a while. Like some have proposed here for the P2 name.
    Then they decided to connect back to their history and remind people of their roots by using "RISC" again. Like some have proposed here for the P2 name.

    Anyway Roman Numerals are in now a days. :)
  • I think it needs a small sticker,

    "FORTH
    inside".

    : )
  • I like the P2 with racing stripes logo because it's eye catching.

    +1

    It additionally indicates that performance can be expected :)


    Novel Solutions - http://www.novelsolutionsonline.com/ - Machinery Design • - • Product Development
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  • TorTor Posts: 1,934
    PLX is good. P2 not so good. Prop not so good. IMO.
  • msrobots wrote: »
    and the PLX512-200ND needs 16 stripes.

    Is it possible to sell P2s not passing all tests under a different Logo, say memory error above something, or not all COGs working?

    How high is the usual yield on a wafer between working complete and not so good working? Can some of the waste be resurrected?

    Mike

    On Semi is going to have a pass/fail test. There will be no flexibility there.
  • Cluso99 wrote: »
    My vote is for
    P2X8C4M64P
    I like the P2 with racing stripes logo because it's eye catching.
    I like the P2X prefix because its easy to remember, and should provide a reasonable search, and prefix for other P2X style chip families.
    I like the 8C4M64P because that describes the features.

    I'm with Cluso99 on this one.
    The P2 will be a family of chips so each variable feature needs to be in the name.

    J
  • Heater.Heater. Posts: 20,832
    edited May 8 Vote Up0Vote Down
    Chip,
    On Semi is going to have a pass/fail test. There will be no flexibility there.
    That sounds reasonable.

    Can we have the ones that fail? Afterall Parallax is paying for them.

    Clive Sinclair built a huge business on failed transistors he got for cheap!

  • Heater. wrote: »
    Chip,
    On Semi is going to have a pass/fail test. There will be no flexibility there.
    That sounds reasonable.

    Can we have the ones that fail? Afterall Parallax is paying for them.

    Clive Sinclair built a huge business on failed transistors he got for cheap!

    On Semi will only ship us good chips. We do not have control before that point.
  • Heater.Heater. Posts: 20,832
    I imagined that was the case. The failed chips would be hard work to do anything with anyway, what with not being packaged. Unlike Sir Clive and his substandard transistors back in the day.

    Makes me wonder though, what is the deal if the yield is terrible? Does OnSemi deliver at an agreed price and suck up the losses or what?



  • cgraceycgracey Posts: 9,139
    edited May 8 Vote Up0Vote Down
    Heater. wrote: »
    ...Makes me wonder though, what is the deal if the yield is terrible? Does OnSemi deliver at an agreed price and suck up the losses or what?


    That is the deal.

    They do a tremendous amount of diligence to ensure that won't happen.
  • Well, you can't always get what you want...

    P2_marking_feedback.png
    718 x 1029 - 36K
  • ... but you get what you need! :-)
  • jmgjmg Posts: 11,661
    cgracey wrote: »
    Well, you can't always get what you want...

    pmrobert wrote: »
    ... but you get what you need! :-)

    :)
    Does this need a package suffix in there, for the TQFP100 ?
    Demand might see a QFN or BGA version offered in the future (same die) ?
    You could ask OnSemi what size BGA package this could drop into ?

  • jmg wrote: »
    cgracey wrote: »
    Well, you can't always get what you want...

    pmrobert wrote: »
    ... but you get what you need! :-)

    :)
    Does this need a package suffix in there, for the TQFP100 ?
    Demand might see a QFN or BGA version offered in the future (same die) ?
    You could ask OnSemi what size BGA package this could drop into ?

    Well, this package is needed for its heat-dissipating ability. Other packages won't have the same ability and won't be usable for this chip. I think this package is going to be the only one.
  • I've asked On Semi to tell me what the limitations are for a customer marking. That way, we can maximize what's available to us.

    Note the wrong pin1 indicator. That's moving to the upper left where it belongs.
  • jmgjmg Posts: 11,661
    edited May 9 Vote Up0Vote Down
    cgracey wrote: »
    jmg wrote: »
    cgracey wrote: »
    Well, you can't always get what you want...

    pmrobert wrote: »
    ... but you get what you need! :-)

    :)
    Does this need a package suffix in there, for the TQFP100 ?
    Demand might see a QFN or BGA version offered in the future (same die) ?
    You could ask OnSemi what size BGA package this could drop into ?

    Well, this package is needed for its heat-dissipating ability. Other packages won't have the same ability and won't be usable for this chip. I think this package is going to be the only one.

    QFN have a central tab, so should be quite similar or better thermally than e-tqfp, and the BGA has a lot of solder contact area, package-to-PCB.
    BGA is not going to be tiny here, as the die area dictates a minimum area, but it will be smaller than the gull wing routed area.
  • Cluso99Cluso99 Posts: 13,770
    cgracey wrote: »
    Well, you can't always get what you want...

    P2_marking_feedback.png
    Is the font size correct?

    OnSemi letters are bigger than "PARALLAX" and the Part Number.

    I was just about to comment about pin 1 but I see you found that.
  • FYI: TQFP100 parts are very commonly available as CBGA-100 parts. CBGA-100 is a 9x9mm BGA with 0.8mm pitch balls. The TQFP100 package is 14x14mm, so there would be a definite space advantage with offering a CBGA package for the P2 (81mm² versus 196mm²). Food for thought: with a CBGA-100 package, you could make a DIP40 based P2 offering 32I/O...just saying....hint hint....
  • Cluso99Cluso99 Posts: 13,770
    The TQFP100 used has a pad underneath that is used both for all the ground inputs and as a heat sink. BGA removes this feature!
  • evanhevanh Posts: 5,105
    edited May 9 Vote Up0Vote Down
    The Prop2 die is 8.5 x 8.5 usable area I believe. The physical silicon edge will be a little more I presume. Can't see that ever fitting in a 9 x 9 package.

    Maybe if/when there is a smaller Prop2 with less HubRAM ... or process shrink ... or MRAM.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • jmgjmg Posts: 11,661
    Cluso99 wrote: »
    The TQFP100 used has a pad underneath that is used both for all the ground inputs and as a heat sink. BGA removes this feature!
    Any BGA package will have a lot more pads than 100, and so you have very good package to PCB thermal connection.
    The final thermal resistance is more determined by things like copper planes, than the package-PCB part of the thermal lineup.


  • jmgjmg Posts: 11,661
    evanh wrote: »
    The Prop2 die is 8.5 x 8.5 usable area I believe. The physical silicon edge will be a little more I presume. Can't see that ever fitting in a 9 x 9 package.
    BGA packages come in 9x9, 10x10, 11x11, 12x12, 13x13... they can come close to die-sized.

  • evanhevanh Posts: 5,105
    jmg wrote: »
    BGA packages come in 9x9, 10x10, 11x11, 12x12, 13x13... they can come close to die-sized.

    WBA is wanting to fit it between the pins of a DIP40 module though. Presumably he chose the 9 x 9 for that reason.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • jmgjmg Posts: 11,661
    evanh wrote: »
    jmg wrote: »
    BGA packages come in 9x9, 10x10, 11x11, 12x12, 13x13... they can come close to die-sized.

    WBA is wanting to fit it between the pins of a DIP40 module though. Presumably he chose the 9 x 9 for that reason.
    I doubt that market is very large, and anyway a 12mm+ BGA looks to fit fine, under a DIP 40 footprint ?

  • Cluso99Cluso99 Posts: 13,770
    edited May 10 Vote Up0Vote Down
    jmg wrote: »
    Cluso99 wrote: »
    The TQFP100 used has a pad underneath that is used both for all the ground inputs and as a heat sink. BGA removes this feature!
    Any BGA package will have a lot more pads than 100, and so you have very good package to PCB thermal connection.
    The final thermal resistance is more determined by things like copper planes, than the package-PCB part of the thermal lineup.

    Of course!!
    And now you have all the traces in the way of a proper copper plane.

    Anyway, If you want to order say 100,000 I am sure you can get another package ;)
  • Any BGA that has 100 pins will require a multilayer pcb which is fine for volume production but not as easy and cheap for prototyping. Then there is the assembly which needs to be done "just right" which once again is not so easy for prototyping. When I think BGA I think big volume as in at least 10k.

    However the thermal resistance of silicon mounted directly on a metal base which is soldered directly to the copper on a pcb is a lot lot less than BGA which would have no intimate thermal contact from the silicon to a heat sink. Remember, a BGA package is constructed by placing the silicon, whether wire bonded or flipped, onto a multilayer pcb like substrate with solder bumps on the other side.

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  • WBA ConsultingWBA Consulting Posts: 2,795
    edited May 10 Vote Up0Vote Down
    My only comment was to correlate that a direct pin count BGA would be significantly smaller, not provide any other pros/cons. However:

    Regarding thermal/ground concerns: BGAs typically have multiple ground balls to satisfy these concerns as well as offering other top surface materials for heat dissipation. Also, don't forget about heatsinks, etc.
    Regarding die size: If the die is 8.5x8.5, than an appropriate sized BGA package can be used to accommodate and also provide further free balls to address any grounding or heat concerns. This is done routinely with many large BGA packages.
    Regarding DIP40 and 9x9: I was simply making a point that a smaller package would allow for a P1 equivalent P2 module for upgrade purposes of existing products, etc.
    Regarding traces in the way of a copper plane: That is why manufacturers will define exit routing practices. Macom's 72x72, 1,156 ball Crosspoint Switch BGA requires multiple ground planes and signal layers, but in 12 layers, all 1,156 balls can be properly routed (yes, that's an extreme BGA, but proves it is entirely possible for any size BGA, hence their popularity as a package)
    Regarding BGA not cheap and easy for prototyping: I would truly hope that Parallax is not isolating their package offerings for DIY use. In my opinion, that would be a very poor decision by Parallax. A BGA would also open doors for a castellated module with some support hardware on board that would be easier to handle than a TQFP for many people.

    I don't mean to debate anyone on these opinions by no means, but I am sharing my perspective from a weekend hobbyist and weekday Engineering Manager at an EMS provider. I see state of the art designs and very weak designs as a normal part of my daily job.
  • jmgjmg Posts: 11,661
    My only comment was to correlate that a direct pin count BGA would be significantly smaller, not provide any other pros/cons. However:
    ...
    I don't mean to debate anyone on these opinions by no means, but I am sharing my perspective from a weekend hobbyist and weekday Engineering Manager at an EMS provider. I see state of the art designs and very weak designs as a normal part of my daily job.

    Yup, certainly BGA is a question that is easy to ask, and allow for (if practical) at this stage of the flow.
    Once Parallax know it is possible, it is easier to sound out demand, and answer customer enquiries.

  • evanhevanh Posts: 5,105
    I think Prop2 I/O count was intentionally kept low to stay within a manageable package for hobbyists. And I also remember mention of thermal cycling being a reason. Soldered BGA, like QFN, will fracture its joints under thermal cycling.

    "Are we alone in the universe?"
    "Yes," said the Oracle.
    "So there's no other life out there?"
    "There is. They're alone too."
  • One only has to look at the poor P1 QFN sales vs QFP to realise that BGA is not likely to be a big seller.
    Just my 2c.
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