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CON wsdly = sys_clk/2500000 DAT ' WS2812 ( array cnt -- ) pin is in cog "pinreg" - line RET is done at HL, not here ' 171207 version reads longs for each LED but only sends 24-bits (change to 32 for WRGB) ' Will transmit a whole array of bytes each back to back in WS2812 timing format ' line idles low and resets/synchs with low =>50us ' A zero is transmitted as 400ns high by 850ns low (+/-150ns) ' A one is transmitted as 800ns high by 450ns low HHL WS2812 mov PTRB,tos1 sub PTRB,#1 'aligns 24-bit values when a long is read .l2 drvh pinreg ' start early as part of looping for each LED rdlong X,PTRB++ ' read next long skip #%110 ' skip delays for 1st bit sent for each LED rep @.led,#24 .lp drvh pinreg ' always clock tx pin high for at least 400ns waitx #wsdly-8 ' 400ns .l1 shl X,#1 wc ' get next bit drvc pinreg ' output data bit waitx #wsdly-2 ' delay again, (data is either high or low) drvl pinreg ' always needs to go low in the last third of the cycle waitx #wsdly-18 .led djnz tos,#.l2 ' read the next long as long as we can (tos = count) .end jmp #DROP2 ' tx line left low to synch - discard stack parameters, all done.
$1.0000 == ledbuf 21 PIN pub LED! ( color led -- ) 4* ledbuf + ! pub SHOW ledbuf 40 WS2812 ;