SRAM Compiler RHEA claims density improvement up to 30%

Some recent comments on SRAM compilers, and processes they support ... I see 180nm mentioned.

https://www10.edacafe.com/nbc/articles/1/1552124/Breakthrough-innovation-TSMC-180-nm-BCD-Gen-2-process-Up-30-savings-silicon-area-with-new-SpRAM-RHEA

https://www.dolphin-integration.com/index.php/silicon_ip/ip_products/description/libraries/SpRAM-RHEA-DV-HD-RR_TSMC_55nm_uLP;SpRAM-RHEA-DV-HD-RR_TSMC_55nm_uLP-eF

Claims "Thanks to its innovative architecture, the density of RAMs has improved by up to 30% and dynamic power consumption savings can reach up to 50%."

Sounds like it could be worth asking OnSemi if they have used this compiler on any process, and if it matches the claims.
A 30% density gain on a RAM intensive part like P2, is a worthwhile gain. Means either more RAM, or more logic.
It may be this is tuned solely for Power, and not Speed, but good IP should be able to select either ?


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