"Virtually in parallel"?

The latest issue of Nuts and Volts tries to characterize users of various different microcontrollers and it says this about Propeller users:
Often, they're simply bored with the standard architectures and long for the excitement of multiple cogs running virtually in parallel.
"Virtually"? It seems to me they *actually* run in parallel.

Comments

  • 18 Comments sorted by Date Added Votes
  • David Betz wrote: »
    The latest issue of Nuts and Volts tries to characterize users of various different microcontrollers and it says this about Propeller users:
    Often, they're simply bored with the standard architectures and long for the excitement of multiple cogs running virtually in parallel.
    "Virtually"? It seems to me they *actually* run in parallel.

    Yes, I noticed that last night when I read the article. Errors like that seem to be more common than ever. Definitely has an effect on how seriously I take anything in any media.
    In science there is no authority. There is only experiment.
    Life is unpredictable. Eat dessert first.
  • Strange thing to say. There is nothing "virtual" about COGs, they are real processors. Of course they really run simultaneously, in parallel, as well.
  • Hmm, what would be virtually in parallel? ... First thought is something like Ladder Logic - An emulation of a parallel execution system that only appears that way without close inspection.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • I think virtually parallel means a Barrel processor, like the XMOS.
    The Cogs of the Propeller are real parallel, but hubram access follows also the 'barrel principle'.

    Andy
  • threads?

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • JavaScript?

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • N&V is the publication that "demonstrated" it was Okay to drive a blue LED from an Ardu*n* pin without a resistor (July 2017 Q&A). While I accept without question anything they publish written by a "Parallaxer", they are certainly not without fault.
    Re-inventing the wheel is not a waste of time if, when you are done, you understand why it is round.
    Cool, CA, USA 95614
  • JonnyMacJonnyMac Posts: 5,868
    edited December 3 Vote Up0Vote Down
    I have direct contact with the publisher/editor. I will send her a note. I will also include a corrective statement in my March column (Jan has already been submitted).

    Edit: I've been traveling so I just saw that piece this morning. I find it silly at best, if not outright offensive. Especially...

    "I welcome your take on what a person's preferred board says about them, even if you don't have "hard evidence" to back up your findings."

    What the actual hell? To me, this is a ridiculous statement, especially in the wake of Make CEO Dale Dougherty's public statement that maker Noami Wu was not a real person, but a persona created by a group of males (he has since publicly apologized). Bergeron's parting comment sounds like an invitation to trash talk those who don't use the same processor, and it completely violates the open and inviting spirit of Nuts & Volts and Servo magazines.
    Jon McPhalen
    Hollywood, CA
    It's Jon or JonnyMac -- please do not call me Jonny.
  • Ariba wrote: »
    The Cogs of the Propeller are real parallel, but hubram access follows also the 'barrel principle'.
    True for the Prop1, but Prop2 HubRAM is parallel enough to be called that. While the sequencing enforces no two Cogs can hit a single memory location at once, all Cogs can still hit HubRAM in parallel.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • Ariba wrote: »
    I think virtually parallel means a Barrel processor, like the XMOS.
    The Cogs of the Propeller are real parallel, but hubram access follows also the 'barrel principle'.

    Andy
    Huh? I thought the XMOS cores ran in parallel as well up to a certain number of threads on a single core.

  • David Betz wrote: »
    Ariba wrote: »
    I think virtually parallel means a Barrel processor, like the XMOS.
    The Cogs of the Propeller are real parallel, but hubram access follows also the 'barrel principle'.

    Andy
    Huh? I thought the XMOS cores ran in parallel as well up to a certain number of threads on a single core.
    Okay, I see now. Up to 4 "logical cores" can run at full speed on each "tile". If you run more than 4 logical cores the speed of each core slows down.

  • evanhevanh Posts: 4,428
    edited December 1 Vote Up0Vote Down
    David Betz wrote: »
    Okay, I see now. Up to 4 "logical cores" can run at full speed on each "tile". If you run more than 4 logical cores the speed of each core slows down.
    Logical and virtual are interchangeable terms. Even at full speed, the "logical cores", aka threads, are time sliced execution. So can be called concurrent but not parallel.

    EDIT: What they call a tile is a real core.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    David Betz wrote: »
    Okay, I see now. Up to 4 "logical cores" can run at full speed on each "tile". If you run more than 4 logical cores the speed of each core slows down.
    Logical and virtual are interchangeable terms. Even at full speed, the "logical cores", aka threads, are time sliced execution. So can be called concurrent but not parallel.

    EDIT: What they call a tile is a real core.
    They're not really time sliced. Each core seems to have a four stage pipeline so there is always an instruction in each of the stages. Up to 4 threads run without an interference from the others. In other words, a single logical core will not run any faster than 4 logical cores on a single tile. If you run more than 4 on a single tile you end up time slicing.

  • evanhevanh Posts: 4,428
    edited December 1 Vote Up0Vote Down
    David Betz wrote: »
    They're not really time sliced. Each core seems to have a four stage pipeline so there is always an instruction in each of the stages.
    They're slicing at all times. I'll explain why below. It has pipeline properties because a context state has to be maintained no matter how fast or slow the execution goes. There is eight threads per tile so eight of everything (*1) is needed. In particular, to maintain task isolation, eight physical sets of the processor registers has to exist.
    Up to 4 threads run without an interference from the others. In other words, a single logical core will not run any faster than 4 logical cores on a single tile. If you run more than 4 on a single tile you end up time slicing.
    The reason why it's 4 (actually, I believe that is 5 for later models) is because, like the Prop1, anything shorter and you have to start coding around the instruction fetching order. That can be confusing at the least and introduce potential bugs.

    So, instead of having execution overlapping instruction fetches (and the usually pipelined speed up), they opted for time sliced threads instead.

    You just have to look at the clock rate vs MIPS to see this.

    EDIT: NOTE: (*1) "everything" is too broad a statement. I meant everything that holds a state, like the program counter for example. There is only one execution unit for the whole tile.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    David Betz wrote: »
    They're not really time sliced. Each core seems to have a four stage pipeline so there is always an instruction in each of the stages.
    They're slicing at all times. I'll explain why below. It has pipeline properties because a context state has to be maintained no matter how fast or slow the execution goes. There is eight threads per tile so eight of everything is needed. In particular, to maintain task isolation, eight physical sets of the processor registers has to exist.
    Up to 4 threads run without an interference from the others. In other words, a single logical core will not run any faster than 4 logical cores on a single tile. If you run more than 4 on a single tile you end up time slicing.
    The reason why it's 4 (actually, I believe that is 5 for later models) is because, like the Prop1, anything shorter and you have to start coding around the instruction fetching order. That can be confusing at the least and introduce potential bugs.

    So, instead of having execution overlapping instruction fetches (and the usually pipelined speed up), they opted for time sliced threads instead.

    You just have to look at the clock rate vs MIPS to see this.
    My point is that the clock rate vs MIPS is constant up to 4 logical cores running. After that it decreases with each additional logical core.

  • I'm explaining how that works.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    I'm explaining how that works.
    Okay, thanks! I have a few XMOS boards kicking around but I never found time to do anything with them. The Propeller seems more fun! :-)

  • Virtually parallel means: we are living in a simulation (like in MATRIX) and all the parallel processing we believe so see is just serial multitasking. So there is a deep state machine behind all the stuff and whenever someone tries to fool the system by making one task more important (the MTGA effort) this will result in the breakdown of the whole system. The solution is to create real cooperative parallel propelling systems, in short: P2 ;-) This will allow to use old principles again and will lead to an unprecedented FAX reduction as have never been seen in history.
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