a little teaser

rjo__

If you have been following Rayman's thread you know that we have a teeny tiny technical issue... sure we could just use the right crystal to generate 24MHz... but what fun is that?

Let's say we want to cover the spectrum from 8 to 48MHz with integer steps, how many and which crystals do we need in our bank of switchable crystal?

I'm not sure I could solve this problem. Hell, I'm not sure I can even define it correctlhy... jitter? What is this "jitter" you guys keep talking about. Does it go well will scotch?


Rich

evanh

​NCO​ ​frequency mode will be okay with much lower target frequencies where the dynamic range isn't being stretched. EDIT: And PWM mode works here too.

But for MHz ranges the answer is PLL, or DLL. I don't have any experience with it but the Prop1 has a PLL in each Cog counter I think. Phil advocated for this to be included in the Prop2 as well if I'm not mistaken.

rjo__

Too late for that... or Ken is going to kill someone:)
AND I'm not (at all) in favor of Chip trying to solve this in Verilog just to make the five of us happy:)

On the P1, we just switch out the crystal to the one with the sweet spot in it.

I am just assuming that we are going to be doing that for the P2... EXCEPT that for testing purposes, I don't want to be switching between boards or switching crystals.
Ergo, a little board with switchable crystals... but which ones? And how many?

Sounds like a good product for someone else to make.

If I'm not understanding you, you have to tell me:)

Thanks

Rich

evanh

Well, a little board with a programmable PLL would be a way. There will be ICs on the market for this very purpose.

Phil Pilgrim (PhiPi)

You don't even need a programmable PLL, just an analog-tunable oscillator. The P2 can provide the analog output, to be fed back, wherein it's kept adjusted via a DPLL program.

But a PLL/DPLL option may not help if the 24 MHz clock edges have to align somehow with the system clock for pixel read-in from the video chip.

-Phil

rjo__

get to work.