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How to use smartpin to make 24 MHz? - Page 2 — Parallax Forums

How to use smartpin to make 24 MHz?

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  • bob_g4bby - Thanks for the reply post. Not many people do the RF stuff anymore so any insights are most welcome. I want a decent SSB Ham transceiver that is reasonably easy to manufacture, competitively priced, and fun to operate. I completely ran out of memory with the P1 chip, and so glad to have the new P2Edge module as my main microprocessor now.

    Progress is being made ! see the attached pics for what I am building
    1789 x 1135 - 491K
    2939 x 2286 - 1M
  • Rayman wrote: »
    Has anyone worked out the math?
    I need a 24 MHz clock to feed to a camera module...

    [...]

    I guess it wouldn't be too hard if period were even number of clocks, but I need a period of 3-1/3 clocks...

    Even though P2 is not the best at generating fixed duty cycle square wave outputs, it looks like it could do quite well at phase measurements - maybe all we need is a basic VCO and a filtered dithered analog output to control it? Does anyone have a suggestion of a VCO chip that covers 24MHz and has a "logic compatible" analog input range?

    It so happens that I also need a clean 24MHz, and can't run the main clock at an integer multiple since I have even tighter requirements for other digital outputs that change state at clock transitions...
  • evanhevanh Posts: 10,437
    Just move one of the frequencies to make sysclock an integer multiple of both. It's unlikely that feeding a slightly off, eg: 24.5 MHz, into the camera is going to be an issue for the camera.

  • jmgjmg Posts: 14,595
    kuba wrote: »
    Even though P2 is not the best at generating fixed duty cycle square wave outputs, it looks like it could do quite well at phase measurements - maybe all we need is a basic VCO and a filtered dithered analog output to control it? Does anyone have a suggestion of a VCO chip that covers 24MHz and has a "logic compatible" analog input range?

    the 4046 family CMOS parts should manage 24MHz VCO.
    You can use ceramic resonators with this part, for a narrow lock range and lower jitter, or you could use a ceramic resonator as a jitter reduction element.
    kuba wrote: »
    It so happens that I also need a clean 24MHz, and can't run the main clock at an integer multiple since I have even tighter requirements for other digital outputs that change state at clock transitions...

    What does 'clean' mean here ? What SysCLK must you have ?
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