Pins

A few questions about the pins:

1. Is the pinout going to be as shown for the 100-pin packages here:
http://forums.parallax.com/discussion/164364/prop2-family/p1 ?

2. Do the pins have weak pull-up or pull-down resistors?

3. Is the maximum clamp diode current the same as for the P1 at 500 µA?

4. Are the pin outputs disabled immediately RESn goes low?

5. If USB programming is to be supported on boot-up which pins would it use?

Formerly known as TonyB

Comments

  • 9 Comments sorted by Date Added Votes
  • threadzthreadz Posts: 44
    edited October 12 Vote Up0Vote Down
    1. Yes, unless a the fab requires a change to make it work, but it probably won't.

    2. Both/neither/better. Each smart pin can have it's high and low state connected to VCC and GND directly, or through any of the following: 1.5Kohm resistor, 15Kohm resistor, 150Kohm resistor, 1mA current limiter, 100uA current limiter, or 10uA current limiter. Also, wheather the HIGH and LOW state means the pin is connected to VCC or GND can be reversed, and either state can also be floating (ie, not connected to anything).
    In theory, you could have a pin's HIGH state connect it to a 100uA current limiter to ground and it's LOW state be a 1.5Kohm pullup resistor to VCC. I have no clue when you would use most of these functions but they're still pretty damn awesome in my opinion.

    3. idk. i didn't even know there were clamp diodes on the P1. Actually, you might be able to use the previous thing as an adjustable clamp diode of sorts.

    4. no, it takes until after the minimum RESn down time for the reset to activate (which i believe is 100uS), this is a measure to prevent noise from causing a reset. After that, all pins are brought to either low or float

    5. USB programming is not implemented so far, but the ROM is not finalized so fingers crossed.
  • Chip made up a table of what's in the custom pin section. I've struggled to intepret it. I'm not sure if those HHH/LLL options can do a true pull-up/down independent of the OUT state. See attached.
    1709 x 894 - 67K
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    ... I'm not sure if those HHH/LLL options can do a true pull-up/down independent of the OUT state.

    Other considerations are
    * does the pin-config of pull-up/down apply during reset
    Other MCUs define such details via the Fuses options....

    TonyB_ wrote: »
    2. Do the pins have weak pull-up or pull-down resistors?
    See above, you can config the pin, but less clear is how that config applies during reset.

    TonyB_ wrote: »
    3. Is the maximum clamp diode current the same as for the P1 at 500 µA?
    That's usually more nominal, than near any damage level.
    The fish hooks to watch for are
    * Lateral currents can flow while a pin is clamping, thereby injecting current into an adjacent pin, which will disturb an ADC reading.
    * Inject too much current, and you can pull Vcc up!! - that will fry the device.. 30 pins at 500uA, is 15mA which is likely more than P2 sinks during reset/boot.

    TonyB_ wrote: »
    4. Are the pin outputs disabled immediately RESn goes low?
    There is a glitch filter, but I think the pins are clocked too,

    Chip would know the time from reset rise, to defined pin-state.
    As above, I don't think pullup/pull down apply during reset. IIRC pins simply float.

  • We first have to find out if there really is any pull-up/down at all. I'm suspecting all those options are only for output drive strengths. And I suspect Chip has assigned pull-up/down to "put a resistor on the board".
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • evanh wrote: »
    We first have to find out if there really is any pull-up/down at all.

    I think they are there, as 'real resistors' not weak fets, and the 15k and 1.5k need to be reasonably precise (5% IIRC) for the USB signaling task.
  • On RESn = low, all pins float after 100ns (due to analog glitch filter on RESn).

    It is your sofltware that configures those resistor-drive and curent-drive modes. To effect a pull-up, you'd set HHH to a resistor or current mode and then output a high. Then, the pin would still work as an input, while weakly driving high. It only takes one WRPIN instruction to change the drive mode
  • evanhevanh Posts: 4,450
    edited October 13 Vote Up0Vote Down
    Okay, it's not a passive pull-up/down, as I expected. I'm starting figure it I think, the dual drive settings look cool. It could emulate an open-collector (within the supply rails) for example - Set HHH to 111 (float) and set LLL to 000 (fast). That impresses me.

    Of course, one reason open-collector gets used is for direct level shifting - which this won't be able to handle.
    The Prisoner's Dilemma, in english - "Selfishness beats altruism within groups. Altruistic groups beat selfish groups." - Quoted part from 2007, D.S Wilson/E.O Wilson.
  • cgraceycgracey Posts: 8,416
    edited October 13 Vote Up0Vote Down
    evanh wrote: »
    ...Of course, one reason open-collector gets used is for direct level shifting - which this won't be able to handle.

    You can output 1's using a settable 8-bit DAC level, with 0's being DAC level $00. Then, you can input using a comparator attached to a separate internal 8-bit reference DAC. So, your digital high output can be set in 13mV increments, and your digital input theshold can be set in 13mV increments.
  • cgracey wrote: »
    You can output 1's using a settable 8-bit DAC level, with 0's being DAC level $00. Then, you can input using a comparator attached to a separate internal 8-bit reference DAC. So, your digital high output can be set in 13mV increments, and your digital input theshold can be set in 13mV increments.
    Neat!
    Looking forward to playing with P2's analog features. :)
    Melbourne, Australia
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